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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index f29c810e..85403767 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -304,6 +304,11 @@ enum {
304 GK20A_PMU_DMAIDX_END = 7 304 GK20A_PMU_DMAIDX_END = 7
305}; 305};
306 306
307struct falc_u64 {
308 u32 lo;
309 u32 hi;
310};
311
307struct falc_dma_addr { 312struct falc_dma_addr {
308 u32 dma_base; 313 u32 dma_base;
309 /*dma_base1 is 9-bit MSB for FB Base 314 /*dma_base1 is 9-bit MSB for FB Base
@@ -708,6 +713,8 @@ struct pmu_pg_cmd {
708enum { 713enum {
709 PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0 , 714 PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0 ,
710 PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, 715 PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
716 PMU_ACR_CMD_ID_RESERVED,
717 PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS,
711}; 718};
712 719
713/* 720/*
@@ -729,14 +736,27 @@ struct pmu_acr_cmd_bootstrap_falcon {
729 u32 falconid; 736 u32 falconid;
730}; 737};
731 738
739/*
740 * falcon ID to bootstrap
741 */
742struct pmu_acr_cmd_bootstrap_multiple_falcons {
743 u8 cmd_type;
744 u32 flags;
745 u32 falconidmask;
746 u32 usevamask;
747 struct falc_u64 wprvirtualbase;
748};
749
732#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 750#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1
733#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 751#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0
734 752
753
735struct pmu_acr_cmd { 754struct pmu_acr_cmd {
736 union { 755 union {
737 u8 cmd_type; 756 u8 cmd_type;
738 struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; 757 struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon;
739 struct pmu_acr_cmd_init_wpr_details init_wpr; 758 struct pmu_acr_cmd_init_wpr_details init_wpr;
759 struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons;
740 }; 760 };
741}; 761};
742 762
@@ -1177,6 +1197,7 @@ struct pmu_gk20a {
1177 /* TBD: remove this if ZBC seq is fixed */ 1197 /* TBD: remove this if ZBC seq is fixed */
1178 struct mem_desc seq_buf; 1198 struct mem_desc seq_buf;
1179 struct mem_desc trace_buf; 1199 struct mem_desc trace_buf;
1200 struct mem_desc wpr_buf;
1180 bool buf_loaded; 1201 bool buf_loaded;
1181 1202
1182 struct pmu_sha1_gid gid_info; 1203 struct pmu_sha1_gid gid_info;
@@ -1294,4 +1315,6 @@ int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
1294void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable); 1315void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable);
1295int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, 1316int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout,
1296 u32 *var, u32 val); 1317 u32 *var, u32 val);
1318void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
1319 void *param, u32 handle, u32 status);
1297#endif /*__PMU_GK20A_H__*/ 1320#endif /*__PMU_GK20A_H__*/