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path: root/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c34
1 files changed, 0 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 86cb04d9..f231e088 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -490,40 +490,6 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set)
490 } 490 }
491} 491}
492 492
493int gk20a_init_pmu_setup_hw1(struct gk20a *g)
494{
495 struct nvgpu_pmu *pmu = &g->pmu;
496 int err = 0;
497
498 nvgpu_log_fn(g, " ");
499
500 nvgpu_mutex_acquire(&pmu->isr_mutex);
501 nvgpu_flcn_reset(pmu->flcn);
502 pmu->isr_enabled = true;
503 nvgpu_mutex_release(&pmu->isr_mutex);
504
505 /* setup apertures - virtual */
506 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
507 pwr_fbif_transcfg_mem_type_virtual_f());
508 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
509 pwr_fbif_transcfg_mem_type_virtual_f());
510 /* setup apertures - physical */
511 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
512 pwr_fbif_transcfg_mem_type_physical_f() |
513 pwr_fbif_transcfg_target_local_fb_f());
514 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
515 pwr_fbif_transcfg_mem_type_physical_f() |
516 pwr_fbif_transcfg_target_coherent_sysmem_f());
517 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
518 pwr_fbif_transcfg_mem_type_physical_f() |
519 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
520
521 err = g->ops.pmu.pmu_nsbootstrap(pmu);
522
523 return err;
524
525}
526
527void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) 493void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
528{ 494{
529 gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); 495 gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr);