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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c17
1 files changed, 4 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 38b8da9c..7df0c71c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -3642,19 +3642,10 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id)
3642 3642
3643 gk20a_dbg_fn(""); 3643 gk20a_dbg_fn("");
3644 3644
3645 if (tegra_cpu_is_asim()) { 3645 gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id),
3646 /* TBD: calculate threshold for silicon */ 3646 PMU_PG_IDLE_THRESHOLD);
3647 gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id), 3647 gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id),
3648 PMU_PG_IDLE_THRESHOLD_SIM); 3648 PMU_PG_POST_POWERUP_IDLE_THRESHOLD);
3649 gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id),
3650 PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM);
3651 } else {
3652 /* TBD: calculate threshold for silicon */
3653 gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id),
3654 PMU_PG_IDLE_THRESHOLD);
3655 gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id),
3656 PMU_PG_POST_POWERUP_IDLE_THRESHOLD);
3657 }
3658 3649
3659 if (g->ops.pmu.pmu_pg_init_param) 3650 if (g->ops.pmu.pmu_pg_init_param)
3660 g->ops.pmu.pmu_pg_init_param(g, pg_engine_id); 3651 g->ops.pmu.pmu_pg_init_param(g, pg_engine_id);