diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_common.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_common.h | 48 |
1 files changed, 1 insertions, 47 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_common.h b/drivers/gpu/nvgpu/gk20a/pmu_common.h index de37caeb..3b3362c1 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_common.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_common.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -72,24 +72,6 @@ struct pmu_dmem { | |||
72 | u32 offset; | 72 | u32 offset; |
73 | }; | 73 | }; |
74 | 74 | ||
75 | /* Make sure size of this structure is a multiple of 4 bytes */ | ||
76 | struct pmu_cmdline_args_v0 { | ||
77 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
78 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | ||
79 | u32 falc_trace_dma_base; /* 256-byte block address */ | ||
80 | u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */ | ||
81 | struct pmu_mem_v0 gc6_ctx; /* dmem offset of gc6 context */ | ||
82 | }; | ||
83 | |||
84 | struct pmu_cmdline_args_v1 { | ||
85 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
86 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | ||
87 | u32 falc_trace_dma_base; /* 256-byte block address */ | ||
88 | u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */ | ||
89 | u8 secure_mode; | ||
90 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | ||
91 | }; | ||
92 | |||
93 | struct flcn_u64 { | 75 | struct flcn_u64 { |
94 | u32 lo; | 76 | u32 lo; |
95 | u32 hi; | 77 | u32 hi; |
@@ -148,34 +130,6 @@ typedef u8 flcn_status; | |||
148 | 130 | ||
149 | #define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1)) | 131 | #define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1)) |
150 | 132 | ||
151 | /*! | ||
152 | * Falcon PMU DMA's minimum size in bytes. | ||
153 | */ | ||
154 | #define PMU_DMA_MIN_READ_SIZE_BYTES 16 | ||
155 | #define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 | ||
156 | |||
157 | #define PMU_FB_COPY_RW_ALIGNMENT \ | ||
158 | (PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES ? \ | ||
159 | PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) | ||
160 | |||
161 | /*! | ||
162 | * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned | ||
163 | * data structures to issue DMA read/write operations. | ||
164 | */ | ||
165 | #define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ | ||
166 | union name##_aligned { \ | ||
167 | struct name data; \ | ||
168 | u8 pad[ALIGN_UP(sizeof(struct name), \ | ||
169 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
170 | } | ||
171 | |||
172 | #define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ | ||
173 | union name##_aligned { \ | ||
174 | union name data; \ | ||
175 | u8 pad[ALIGN_UP(sizeof(union name), \ | ||
176 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
177 | } | ||
178 | |||
179 | #define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) | 133 | #define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) |
180 | 134 | ||
181 | #endif | 135 | #endif |