summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/pmu_api.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_api.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_api.h469
1 files changed, 0 insertions, 469 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h
index d4af6bdb..6284f2f9 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_api.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h
@@ -17,253 +17,6 @@
17#include <nvgpu/flcnif_cmn.h> 17#include <nvgpu/flcnif_cmn.h>
18#include "pmuif/gpmuif_pg_rppg.h" 18#include "pmuif/gpmuif_pg_rppg.h"
19 19
20/* PMU Command/Message Interfaces for Adaptive Power */
21/* Macro to get Histogram index */
22#define PMU_AP_HISTOGRAM(idx) (idx)
23#define PMU_AP_HISTOGRAM_CONT (4)
24
25/* Total number of histogram bins */
26#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
27
28/* Mapping between Idle counters and histograms */
29#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
30#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
31#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
32#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
33
34
35/* Mapping between AP_CTRLs and Histograms */
36#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
37
38/* Mapping between AP_CTRLs and Idle counters */
39#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
40
41/* Adaptive Power Controls (AP_CTRL) */
42enum {
43 PMU_AP_CTRL_ID_GRAPHICS = 0x0,
44 PMU_AP_CTRL_ID_MAX,
45};
46
47/* AP_CTRL Statistics */
48struct pmu_ap_ctrl_stat {
49 /*
50 * Represents whether AP is active or not
51 */
52 u8 b_active;
53
54 /* Idle filter represented by histogram bin index */
55 u8 idle_filter_x;
56 u8 rsvd[2];
57
58 /* Total predicted power saving cycles. */
59 s32 power_saving_h_cycles;
60
61 /* Counts how many times AP gave us -ve power benefits. */
62 u32 bad_decision_count;
63
64 /*
65 * Number of times ap structure needs to skip AP iterations
66 * KICK_CTRL from kernel updates this parameter.
67 */
68 u32 skip_count;
69 u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
70};
71
72/* Parameters initialized by INITn APCTRL command */
73struct pmu_ap_ctrl_init_params {
74 /* Minimum idle filter value in Us */
75 u32 min_idle_filter_us;
76
77 /*
78 * Minimum Targeted Saving in Us. AP will update idle thresholds only
79 * if power saving achieved by updating idle thresholds is greater than
80 * Minimum targeted saving.
81 */
82 u32 min_target_saving_us;
83
84 /* Minimum targeted residency of power feature in Us */
85 u32 power_break_even_us;
86
87 /*
88 * Maximum number of allowed power feature cycles per sample.
89 *
90 * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
91 * AKA pgPerSampleMax in original algorithm.
92 */
93 u32 cycles_per_sample_max;
94};
95
96/* AP Commands/Message structures */
97
98/*
99 * Structure for Generic AP Commands
100 */
101struct pmu_ap_cmd_common {
102 u8 cmd_type;
103 u16 cmd_id;
104};
105
106/*
107 * Structure for INIT AP command
108 */
109struct pmu_ap_cmd_init {
110 u8 cmd_type;
111 u16 cmd_id;
112 u8 rsvd;
113 u32 pg_sampling_period_us;
114};
115
116/*
117 * Structure for Enable/Disable ApCtrl Commands
118 */
119struct pmu_ap_cmd_enable_ctrl {
120 u8 cmd_type;
121 u16 cmd_id;
122
123 u8 ctrl_id;
124};
125
126struct pmu_ap_cmd_disable_ctrl {
127 u8 cmd_type;
128 u16 cmd_id;
129
130 u8 ctrl_id;
131};
132
133/*
134 * Structure for INIT command
135 */
136struct pmu_ap_cmd_init_ctrl {
137 u8 cmd_type;
138 u16 cmd_id;
139 u8 ctrl_id;
140 struct pmu_ap_ctrl_init_params params;
141};
142
143struct pmu_ap_cmd_init_and_enable_ctrl {
144 u8 cmd_type;
145 u16 cmd_id;
146 u8 ctrl_id;
147 struct pmu_ap_ctrl_init_params params;
148};
149
150/*
151 * Structure for KICK_CTRL command
152 */
153struct pmu_ap_cmd_kick_ctrl {
154 u8 cmd_type;
155 u16 cmd_id;
156 u8 ctrl_id;
157
158 u32 skip_count;
159};
160
161/*
162 * Structure for PARAM command
163 */
164struct pmu_ap_cmd_param {
165 u8 cmd_type;
166 u16 cmd_id;
167 u8 ctrl_id;
168
169 u32 data;
170};
171
172/*
173 * Defines for AP commands
174 */
175enum {
176 PMU_AP_CMD_ID_INIT = 0x0,
177 PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
178 PMU_AP_CMD_ID_ENABLE_CTRL,
179 PMU_AP_CMD_ID_DISABLE_CTRL,
180 PMU_AP_CMD_ID_KICK_CTRL,
181};
182
183/*
184 * AP Command
185 */
186union pmu_ap_cmd {
187 u8 cmd_type;
188 struct pmu_ap_cmd_common cmn;
189 struct pmu_ap_cmd_init init;
190 struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
191 struct pmu_ap_cmd_enable_ctrl enable_ctrl;
192 struct pmu_ap_cmd_disable_ctrl disable_ctrl;
193 struct pmu_ap_cmd_kick_ctrl kick_ctrl;
194};
195
196/*
197 * Structure for generic AP Message
198 */
199struct pmu_ap_msg_common {
200 u8 msg_type;
201 u16 msg_id;
202};
203
204/*
205 * Structure for INIT_ACK Message
206 */
207struct pmu_ap_msg_init_ack {
208 u8 msg_type;
209 u16 msg_id;
210 u8 ctrl_id;
211 u32 stats_dmem_offset;
212};
213
214/*
215 * Defines for AP messages
216 */
217enum {
218 PMU_AP_MSG_ID_INIT_ACK = 0x0,
219};
220
221/*
222 * AP Message
223 */
224union pmu_ap_msg {
225 u8 msg_type;
226 struct pmu_ap_msg_common cmn;
227 struct pmu_ap_msg_init_ack init_ack;
228};
229
230/* Default Sampling Period of AELPG */
231#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
232
233/* Default values of APCTRL parameters */
234#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
235#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
236#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
237#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
238
239/*
240 * Disable reason for Adaptive Power Controller
241 */
242enum {
243 APCTRL_DISABLE_REASON_RM_UNLOAD,
244 APCTRL_DISABLE_REASON_RMCTRL,
245};
246
247/*
248 * Adaptive Power Controller
249 */
250struct ap_ctrl {
251 u32 stats_dmem_offset;
252 u32 disable_reason_mask;
253 struct pmu_ap_ctrl_stat stat_cache;
254 u8 b_ready;
255};
256
257/*
258 * Adaptive Power structure
259 *
260 * ap structure provides generic infrastructure to make any power feature
261 * adaptive.
262 */
263struct pmu_ap {
264 u32 supported_mask;
265 struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
266};
267/*---------------------------------------------------------*/ 20/*---------------------------------------------------------*/
268 21
269/*perfmon task defines*/ 22/*perfmon task defines*/
@@ -399,228 +152,6 @@ struct pmu_perfmon_msg {
399 struct pmu_perfmon_msg_generic gen; 152 struct pmu_perfmon_msg_generic gen;
400 }; 153 };
401}; 154};
402/*---------------------------------------------------------*/
403/*ELPG/PG defines*/
404enum {
405 PMU_PG_ELPG_MSG_INIT_ACK,
406 PMU_PG_ELPG_MSG_DISALLOW_ACK,
407 PMU_PG_ELPG_MSG_ALLOW_ACK,
408 PMU_PG_ELPG_MSG_FREEZE_ACK,
409 PMU_PG_ELPG_MSG_FREEZE_ABORT,
410 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
411};
412
413struct pmu_pg_msg_elpg_msg {
414 u8 msg_type;
415 u8 engine_id;
416 u16 msg;
417};
418
419enum {
420 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
421};
422
423struct pmu_pg_msg_stat {
424 u8 msg_type;
425 u8 engine_id;
426 u16 sub_msg_id;
427 u32 data;
428};
429
430enum {
431 PMU_PG_MSG_ENG_BUF_LOADED,
432 PMU_PG_MSG_ENG_BUF_UNLOADED,
433 PMU_PG_MSG_ENG_BUF_FAILED,
434};
435
436struct pmu_pg_msg_eng_buf_stat {
437 u8 msg_type;
438 u8 engine_id;
439 u8 buf_idx;
440 u8 status;
441};
442
443struct pmu_pg_msg {
444 union {
445 u8 msg_type;
446 struct pmu_pg_msg_elpg_msg elpg_msg;
447 struct pmu_pg_msg_stat stat;
448 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
449 /* TBD: other pg messages */
450 union pmu_ap_msg ap_msg;
451 struct nv_pmu_rppg_msg rppg_msg;
452 };
453};
454
455enum {
456 PMU_PG_ELPG_CMD_INIT,
457 PMU_PG_ELPG_CMD_DISALLOW,
458 PMU_PG_ELPG_CMD_ALLOW,
459 PMU_PG_ELPG_CMD_FREEZE,
460 PMU_PG_ELPG_CMD_UNFREEZE,
461};
462
463enum {
464 PMU_PG_CMD_ID_ELPG_CMD = 0,
465 PMU_PG_CMD_ID_ENG_BUF_LOAD,
466 PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
467 PMU_PG_CMD_ID_PG_STAT,
468 PMU_PG_CMD_ID_PG_LOG_INIT,
469 PMU_PG_CMD_ID_PG_LOG_FLUSH,
470 PMU_PG_CMD_ID_PG_PARAM,
471 PMU_PG_CMD_ID_ELPG_INIT,
472 PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
473 PMU_PG_CMD_ID_ELPG_ABORT_POLL,
474 PMU_PG_CMD_ID_ELPG_PWR_UP,
475 PMU_PG_CMD_ID_ELPG_DISALLOW,
476 PMU_PG_CMD_ID_ELPG_ALLOW,
477 PMU_PG_CMD_ID_AP,
478 RM_PMU_PG_CMD_ID_PSI,
479 RM_PMU_PG_CMD_ID_CG,
480 PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
481 PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
482 PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
483 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
484 PMU_PMU_PG_CMD_ID_RPPG = 0x24,
485};
486
487struct pmu_pg_cmd_elpg_cmd {
488 u8 cmd_type;
489 u8 engine_id;
490 u16 cmd;
491};
492
493struct pmu_pg_cmd_eng_buf_load_v0 {
494 u8 cmd_type;
495 u8 engine_id;
496 u8 buf_idx;
497 u8 pad;
498 u16 buf_size;
499 u32 dma_base;
500 u8 dma_offset;
501 u8 dma_idx;
502};
503
504struct pmu_pg_cmd_eng_buf_load_v1 {
505 u8 cmd_type;
506 u8 engine_id;
507 u8 buf_idx;
508 u8 pad;
509 struct flcn_mem_desc {
510 struct falc_u64 dma_addr;
511 u16 dma_size;
512 u8 dma_idx;
513 } dma_desc;
514};
515
516struct pmu_pg_cmd_eng_buf_load_v2 {
517 u8 cmd_type;
518 u8 engine_id;
519 u8 buf_idx;
520 u8 pad;
521 struct flcn_mem_desc_v0 dma_desc;
522};
523
524enum {
525 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
526};
527
528#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
529#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01
530#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04
531#define PMU_PG_PARAM_CMD_POST_INIT 0x06
532
533#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
534#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
535#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3)
536
537#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3)
538#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
539 ( \
540 NVGPU_PMU_GR_FEATURE_MASK_RPPG \
541 )
542
543#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0)
544#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1)
545#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8)
546#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5)
547
548#define NVGPU_PMU_MS_FEATURE_MASK_ALL \
549 ( \
550 NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\
551 NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\
552 NVGPU_PMU_MS_FEATURE_MASK_RPPG |\
553 NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \
554 )
555
556#define PG_REQUEST_TYPE_GLOBAL 0x0
557#define PG_REQUEST_TYPE_PSTATE 0x1
558
559struct pmu_pg_cmd_gr_init_param {
560 u8 cmd_type;
561 u16 sub_cmd_id;
562 u8 featuremask;
563};
564
565struct pmu_pg_cmd_ms_init_param {
566 u8 cmd_type;
567 u16 cmd_id;
568 u8 psi;
569 u8 idle_flipped_test_enabled;
570 u16 psiSettleTimeUs;
571 u8 rsvd[2];
572 u32 support_mask;
573 u32 abort_timeout_us;
574};
575
576struct pmu_pg_cmd_mclk_change {
577 u8 cmd_type;
578 u16 cmd_id;
579 u8 rsvd;
580 u32 data;
581};
582
583#define PG_VOLT_RAIL_IDX_MAX 2
584
585struct pmu_pg_volt_rail {
586 u8 volt_rail_idx;
587 u8 sleep_volt_dev_idx;
588 u8 sleep_vfe_idx;
589 u32 sleep_voltage_uv;
590 u32 therm_vid0_cache;
591 u32 therm_vid1_cache;
592};
593
594struct pmu_pg_cmd_post_init_param {
595 u8 cmd_type;
596 u16 cmd_id;
597 struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
598};
599
600struct pmu_pg_cmd_stat {
601 u8 cmd_type;
602 u8 engine_id;
603 u16 sub_cmd_id;
604 u32 data;
605};
606
607struct pmu_pg_cmd {
608 union {
609 u8 cmd_type;
610 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
611 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
612 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
613 struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
614 struct pmu_pg_cmd_stat stat;
615 struct pmu_pg_cmd_gr_init_param gr_init_param;
616 struct pmu_pg_cmd_ms_init_param ms_init_param;
617 struct pmu_pg_cmd_mclk_change mclk_change;
618 struct pmu_pg_cmd_post_init_param post_init;
619 /* TBD: other pg commands */
620 union pmu_ap_cmd ap_cmd;
621 struct nv_pmu_rppg_cmd rppg_cmd;
622 };
623};
624 155
625/*---------------------------------------------------------*/ 156/*---------------------------------------------------------*/
626/* ACR Commands/Message structures */ 157/* ACR Commands/Message structures */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 23:09:19 -0400