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path: root/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mm_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c25
1 files changed, 4 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index eaf8f74a..b9217c2c 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -42,12 +42,13 @@
42#include "mm_gk20a.h" 42#include "mm_gk20a.h"
43#include "fence_gk20a.h" 43#include "fence_gk20a.h"
44#include "kind_gk20a.h" 44#include "kind_gk20a.h"
45#include "bus_gk20a.h"
45 46
46#include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h> 47#include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h>
47#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
48#include <nvgpu/hw/gk20a/hw_ram_gk20a.h> 48#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
49#include <nvgpu/hw/gk20a/hw_pram_gk20a.h> 49#include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
50#include <nvgpu/hw/gk20a/hw_mc_gk20a.h> 50#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
51#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
51#include <nvgpu/hw/gk20a/hw_flush_gk20a.h> 52#include <nvgpu/hw/gk20a/hw_flush_gk20a.h>
52#include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> 53#include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
53 54
@@ -1087,8 +1088,8 @@ int gk20a_init_mm_setup_hw(struct gk20a *g)
1087 1088
1088 g->ops.fb.init_hw(g); 1089 g->ops.fb.init_hw(g);
1089 1090
1090 if (g->ops.mm.bar1_bind) 1091 if (g->ops.bus.bar1_bind)
1091 g->ops.mm.bar1_bind(g, &mm->bar1.inst_block); 1092 g->ops.bus.bar1_bind(g, &mm->bar1.inst_block);
1092 1093
1093 if (g->ops.mm.init_bar2_mm_hw_setup) { 1094 if (g->ops.mm.init_bar2_mm_hw_setup) {
1094 err = g->ops.mm.init_bar2_mm_hw_setup(g); 1095 err = g->ops.mm.init_bar2_mm_hw_setup(g);
@@ -1103,23 +1104,6 @@ int gk20a_init_mm_setup_hw(struct gk20a *g)
1103 return 0; 1104 return 0;
1104} 1105}
1105 1106
1106static int gk20a_mm_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst)
1107{
1108 u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
1109 u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a());
1110
1111 gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v);
1112
1113 gk20a_writel(g, bus_bar1_block_r(),
1114 gk20a_aperture_mask(g, bar1_inst,
1115 bus_bar1_block_target_sys_mem_ncoh_f(),
1116 bus_bar1_block_target_vid_mem_f()) |
1117 bus_bar1_block_mode_virtual_f() |
1118 bus_bar1_block_ptr_f(ptr_v));
1119
1120 return 0;
1121}
1122
1123int gk20a_init_mm_support(struct gk20a *g) 1107int gk20a_init_mm_support(struct gk20a *g)
1124{ 1108{
1125 u32 err; 1109 u32 err;
@@ -5447,7 +5431,6 @@ void gk20a_init_mm(struct gpu_ops *gops)
5447 gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; 5431 gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;
5448 gops->mm.init_pdb = gk20a_mm_init_pdb; 5432 gops->mm.init_pdb = gk20a_mm_init_pdb;
5449 gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; 5433 gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw;
5450 gops->mm.bar1_bind = gk20a_mm_bar1_bind;
5451 gops->mm.init_inst_block = gk20a_init_inst_block; 5434 gops->mm.init_inst_block = gk20a_init_inst_block;
5452 gops->mm.is_bar1_supported = gk20a_mm_is_bar1_supported; 5435 gops->mm.is_bar1_supported = gk20a_mm_is_bar1_supported;
5453 gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending; 5436 gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending;