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path: root/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/mc_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/mc_gk20a.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index accda972..e25fcfc3 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -27,13 +27,11 @@
27void mc_gk20a_isr_stall(struct gk20a *g) 27void mc_gk20a_isr_stall(struct gk20a *g)
28{ 28{
29 u32 mc_intr_0; 29 u32 mc_intr_0;
30 int hw_irq_count;
31 u32 engine_id_idx; 30 u32 engine_id_idx;
32 u32 active_engine_id = 0; 31 u32 active_engine_id = 0;
33 u32 engine_enum = ENGINE_INVAL_GK20A; 32 u32 engine_enum = ENGINE_INVAL_GK20A;
34 33
35 mc_intr_0 = g->ops.mc.intr_stall(g); 34 mc_intr_0 = g->ops.mc.intr_stall(g);
36 hw_irq_count = atomic_read(&g->hw_irq_stall_count);
37 35
38 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); 36 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
39 37
@@ -67,9 +65,6 @@ void mc_gk20a_isr_stall(struct gk20a *g)
67 g->ops.ltc.isr(g); 65 g->ops.ltc.isr(g);
68 if (mc_intr_0 & mc_intr_0_pbus_pending_f()) 66 if (mc_intr_0 & mc_intr_0_pbus_pending_f())
69 g->ops.bus.isr(g); 67 g->ops.bus.isr(g);
70
71 /* sync handled irq counter before re-enabling interrupts */
72 atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
73} 68}
74 69
75void mc_gk20a_intr_enable(struct gk20a *g) 70void mc_gk20a_intr_enable(struct gk20a *g)