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path: root/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h64
1 files changed, 0 insertions, 64 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
index f18e19be..463443d6 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
@@ -2618,30 +2618,6 @@ static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
2618{ 2618{
2619 return 0x10000000; 2619 return 0x10000000;
2620} 2620}
2621static inline u32 gr_gpcs_tpcs_l1c_pm_r(void)
2622{
2623 return 0x00419ca8;
2624}
2625static inline u32 gr_gpcs_tpcs_l1c_pm_enable_m(void)
2626{
2627 return 0x1 << 31;
2628}
2629static inline u32 gr_gpcs_tpcs_l1c_pm_enable_enable_f(void)
2630{
2631 return 0x80000000;
2632}
2633static inline u32 gr_gpcs_tpcs_l1c_cfg_r(void)
2634{
2635 return 0x00419cb8;
2636}
2637static inline u32 gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_m(void)
2638{
2639 return 0x1 << 31;
2640}
2641static inline u32 gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_enable_f(void)
2642{
2643 return 0x80000000;
2644}
2645static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) 2621static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
2646{ 2622{
2647 return 0x00419c00; 2623 return 0x00419c00;
@@ -2654,26 +2630,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
2654{ 2630{
2655 return 0x8; 2631 return 0x8;
2656} 2632}
2657static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void)
2658{
2659 return 0x00419e00;
2660}
2661static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void)
2662{
2663 return 0x1 << 7;
2664}
2665static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void)
2666{
2667 return 0x80;
2668}
2669static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void)
2670{
2671 return 0x1 << 15;
2672}
2673static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void)
2674{
2675 return 0x8000;
2676}
2677static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) 2633static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
2678{ 2634{
2679 return 0x00419e44; 2635 return 0x00419e44;
@@ -2906,14 +2862,6 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
2906{ 2862{
2907 return 0x00419f70; 2863 return 0x00419f70;
2908} 2864}
2909static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_m(void)
2910{
2911 return 0x1 << 1;
2912}
2913static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_enable_f(void)
2914{
2915 return 0x2;
2916}
2917static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) 2865static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
2918{ 2866{
2919 return 0x1 << 4; 2867 return 0x1 << 4;
@@ -2938,18 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
2938{ 2886{
2939 return (v & 0x1) << 0; 2887 return (v & 0x1) << 0;
2940} 2888}
2941static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_m(void)
2942{
2943 return 0x1 << 16;
2944}
2945static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_enable_f(void)
2946{
2947 return 0x10000;
2948}
2949static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void)
2950{
2951 return 0x00419ed0;
2952}
2953static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) 2889static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
2954{ 2890{
2955 return 0x0041be08; 2891 return 0x0041be08;