summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/hal_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/hal_gk20a.c208
1 files changed, 0 insertions, 208 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
deleted file mode 100644
index 5408c822..00000000
--- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
+++ /dev/null
@@ -1,208 +0,0 @@
1/*
2 * drivers/video/tegra/host/gk20a/hal_gk20a.c
3 *
4 * GK20A Tegra HAL interface.
5 *
6 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#include "hal_gk20a.h"
19#include "bus_gk20a.h"
20#include "ltc_gk20a.h"
21#include "fb_gk20a.h"
22#include "gk20a.h"
23#include "gk20a_gating_reglist.h"
24#include "channel_gk20a.h"
25#include "gr_ctx_gk20a.h"
26#include "fecs_trace_gk20a.h"
27#include "mm_gk20a.h"
28#include "mc_gk20a.h"
29#include "flcn_gk20a.h"
30#include "pmu_gk20a.h"
31#include "clk_gk20a.h"
32#include "regops_gk20a.h"
33#include "therm_gk20a.h"
34#include "tsg_gk20a.h"
35#include "dbg_gpu_gk20a.h"
36#include "css_gr_gk20a.h"
37#include "pramin_gk20a.h"
38#include "priv_ring_gk20a.h"
39
40#include <nvgpu/debug.h>
41#include <nvgpu/log.h>
42#include <nvgpu/bug.h>
43
44#include <nvgpu/hw/gk20a/hw_proj_gk20a.h>
45
46static const struct gpu_ops gk20a_ops = {
47 .ltc = {
48 .determine_L2_size_bytes = gk20a_determine_L2_size_bytes,
49 .init_comptags = gk20a_ltc_init_comptags,
50 .cbc_ctrl = gk20a_ltc_cbc_ctrl,
51 .set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry,
52 .set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry,
53 .init_cbc = gk20a_ltc_init_cbc,
54#ifdef CONFIG_DEBUG_FS
55 .sync_debugfs = gk20a_ltc_sync_debugfs,
56#endif
57 .init_fs_state = gk20a_ltc_init_fs_state,
58 .isr = gk20a_ltc_isr,
59 },
60 .clock_gating = {
61 .slcg_gr_load_gating_prod =
62 gr_gk20a_slcg_gr_load_gating_prod,
63 .slcg_perf_load_gating_prod =
64 gr_gk20a_slcg_perf_load_gating_prod,
65 .slcg_ltc_load_gating_prod =
66 ltc_gk20a_slcg_ltc_load_gating_prod,
67 .blcg_gr_load_gating_prod =
68 gr_gk20a_blcg_gr_load_gating_prod,
69 .pg_gr_load_gating_prod =
70 gr_gk20a_pg_gr_load_gating_prod,
71 .slcg_therm_load_gating_prod =
72 gr_gk20a_slcg_therm_load_gating_prod,
73 },
74};
75
76static int gk20a_get_litter_value(struct gk20a *g, int value)
77{
78 int ret = EINVAL;
79 switch (value) {
80 case GPU_LIT_NUM_GPCS:
81 ret = proj_scal_litter_num_gpcs_v();
82 break;
83 case GPU_LIT_NUM_PES_PER_GPC:
84 ret = proj_scal_litter_num_pes_per_gpc_v();
85 break;
86 case GPU_LIT_NUM_ZCULL_BANKS:
87 ret = proj_scal_litter_num_zcull_banks_v();
88 break;
89 case GPU_LIT_NUM_TPC_PER_GPC:
90 ret = proj_scal_litter_num_tpc_per_gpc_v();
91 break;
92 case GPU_LIT_NUM_SM_PER_TPC:
93 ret = 1;
94 break;
95 case GPU_LIT_NUM_FBPS:
96 ret = proj_scal_litter_num_fbps_v();
97 break;
98 case GPU_LIT_GPC_BASE:
99 ret = proj_gpc_base_v();
100 break;
101 case GPU_LIT_GPC_STRIDE:
102 ret = proj_gpc_stride_v();
103 break;
104 case GPU_LIT_GPC_SHARED_BASE:
105 ret = proj_gpc_shared_base_v();
106 break;
107 case GPU_LIT_TPC_IN_GPC_BASE:
108 ret = proj_tpc_in_gpc_base_v();
109 break;
110 case GPU_LIT_TPC_IN_GPC_STRIDE:
111 ret = proj_tpc_in_gpc_stride_v();
112 break;
113 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
114 ret = proj_tpc_in_gpc_shared_base_v();
115 break;
116 case GPU_LIT_PPC_IN_GPC_BASE:
117 ret = proj_ppc_in_gpc_base_v();
118 break;
119 case GPU_LIT_PPC_IN_GPC_STRIDE:
120 ret = proj_ppc_in_gpc_stride_v();
121 break;
122 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
123 ret = proj_ppc_in_gpc_shared_base_v();
124 break;
125 case GPU_LIT_ROP_BASE:
126 ret = proj_rop_base_v();
127 break;
128 case GPU_LIT_ROP_STRIDE:
129 ret = proj_rop_stride_v();
130 break;
131 case GPU_LIT_ROP_SHARED_BASE:
132 ret = proj_rop_shared_base_v();
133 break;
134 case GPU_LIT_HOST_NUM_ENGINES:
135 ret = proj_host_num_engines_v();
136 break;
137 case GPU_LIT_HOST_NUM_PBDMA:
138 ret = proj_host_num_pbdma_v();
139 break;
140 case GPU_LIT_LTC_STRIDE:
141 ret = proj_ltc_stride_v();
142 break;
143 case GPU_LIT_LTS_STRIDE:
144 ret = proj_lts_stride_v();
145 break;
146 /* GK20A does not have a FBPA unit, despite what's listed in the
147 * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS,
148 * so hardcode all values to 0.
149 */
150 case GPU_LIT_NUM_FBPAS:
151 case GPU_LIT_FBPA_STRIDE:
152 case GPU_LIT_FBPA_BASE:
153 case GPU_LIT_FBPA_SHARED_BASE:
154 ret = 0;
155 break;
156 default:
157 nvgpu_err(g, "Missing definition %d", value);
158 BUG();
159 break;
160 }
161
162 return ret;
163}
164
165int gk20a_init_hal(struct gk20a *g)
166{
167 struct gpu_ops *gops = &g->ops;
168 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
169
170 gops->ltc = gk20a_ops.ltc;
171 gops->clock_gating = gk20a_ops.clock_gating;
172 gops->privsecurity = 0;
173 gops->securegpccs = 0;
174 gops->pmupstate = false;
175 gk20a_init_bus(gops);
176 gk20a_init_mc(gops);
177 gk20a_init_priv_ring(gops);
178 gk20a_init_gr_ops(gops);
179 gk20a_init_fecs_trace_ops(gops);
180 gk20a_init_fb(gops);
181 gk20a_init_fifo(gops);
182 gk20a_init_ce2(gops);
183 gk20a_init_gr_ctx(gops);
184 gk20a_init_mm(gops);
185 gk20a_falcon_init_hal(gops);
186 gk20a_init_pmu_ops(gops);
187 gk20a_init_regops(gops);
188 gk20a_init_debug_ops(gops);
189 gk20a_init_dbg_session_ops(gops);
190 gk20a_init_therm_ops(gops);
191 gk20a_init_tsg_ops(gops);
192 gk20a_init_pramin_ops(gops);
193#if defined(CONFIG_GK20A_CYCLE_STATS)
194 gk20a_init_css_ops(gops);
195#endif
196 g->name = "gk20a";
197 gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
198 gops->get_litter_value = gk20a_get_litter_value;
199
200 c->twod_class = FERMI_TWOD_A;
201 c->threed_class = KEPLER_C;
202 c->compute_class = KEPLER_COMPUTE_A;
203 c->gpfifo_class = KEPLER_CHANNEL_GPFIFO_C;
204 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_A;
205 c->dma_copy_class = KEPLER_DMA_COPY_A;
206
207 return 0;
208}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 20:09:04 -0400