diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | 261 |
1 files changed, 261 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h new file mode 100644 index 00000000..d0b6df47 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | |||
@@ -0,0 +1,261 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Context Pri Register Addressing | ||
3 | * | ||
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef GR_PRI_GK20A_H | ||
25 | #define GR_PRI_GK20A_H | ||
26 | |||
27 | /* | ||
28 | * These convenience macros are generally for use in the management/modificaiton | ||
29 | * of the context state store for gr/compute contexts. | ||
30 | */ | ||
31 | |||
32 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | ||
33 | |||
34 | /* | ||
35 | * GPC pri addressing | ||
36 | */ | ||
37 | static inline u32 pri_gpccs_addr_width(void) | ||
38 | { | ||
39 | return 15; /*from where?*/ | ||
40 | } | ||
41 | static inline u32 pri_gpccs_addr_mask(u32 addr) | ||
42 | { | ||
43 | return addr & ((1 << pri_gpccs_addr_width()) - 1); | ||
44 | } | ||
45 | static inline u32 pri_gpc_addr(struct gk20a *g, u32 addr, u32 gpc) | ||
46 | { | ||
47 | u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE); | ||
48 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
49 | return gpc_base + (gpc * gpc_stride) + addr; | ||
50 | } | ||
51 | static inline bool pri_is_gpc_addr_shared(struct gk20a *g, u32 addr) | ||
52 | { | ||
53 | u32 gpc_shared_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_SHARED_BASE); | ||
54 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
55 | return (addr >= gpc_shared_base) && | ||
56 | (addr < gpc_shared_base + gpc_stride); | ||
57 | } | ||
58 | static inline bool pri_is_gpc_addr(struct gk20a *g, u32 addr) | ||
59 | { | ||
60 | u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE); | ||
61 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
62 | u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); | ||
63 | return ((addr >= gpc_base) && | ||
64 | (addr < gpc_base + num_gpcs * gpc_stride)) || | ||
65 | pri_is_gpc_addr_shared(g, addr); | ||
66 | } | ||
67 | static inline u32 pri_get_gpc_num(struct gk20a *g, u32 addr) | ||
68 | { | ||
69 | u32 i, start; | ||
70 | u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); | ||
71 | u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE); | ||
72 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
73 | for (i = 0; i < num_gpcs; i++) { | ||
74 | start = gpc_base + (i * gpc_stride); | ||
75 | if ((addr >= start) && (addr < (start + gpc_stride))) | ||
76 | return i; | ||
77 | } | ||
78 | return 0; | ||
79 | } | ||
80 | |||
81 | /* | ||
82 | * PPC pri addressing | ||
83 | */ | ||
84 | static inline bool pri_is_ppc_addr_shared(struct gk20a *g, u32 addr) | ||
85 | { | ||
86 | u32 ppc_in_gpc_shared_base = nvgpu_get_litter_value(g, | ||
87 | GPU_LIT_PPC_IN_GPC_SHARED_BASE); | ||
88 | u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
89 | GPU_LIT_PPC_IN_GPC_STRIDE); | ||
90 | |||
91 | return ((addr >= ppc_in_gpc_shared_base) && | ||
92 | (addr < (ppc_in_gpc_shared_base + ppc_in_gpc_stride))); | ||
93 | } | ||
94 | |||
95 | static inline bool pri_is_ppc_addr(struct gk20a *g, u32 addr) | ||
96 | { | ||
97 | u32 ppc_in_gpc_base = nvgpu_get_litter_value(g, | ||
98 | GPU_LIT_PPC_IN_GPC_BASE); | ||
99 | u32 num_pes_per_gpc = nvgpu_get_litter_value(g, | ||
100 | GPU_LIT_NUM_PES_PER_GPC); | ||
101 | u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
102 | GPU_LIT_PPC_IN_GPC_STRIDE); | ||
103 | |||
104 | return ((addr >= ppc_in_gpc_base) && | ||
105 | (addr < ppc_in_gpc_base + num_pes_per_gpc * ppc_in_gpc_stride)) | ||
106 | || pri_is_ppc_addr_shared(g, addr); | ||
107 | } | ||
108 | |||
109 | /* | ||
110 | * TPC pri addressing | ||
111 | */ | ||
112 | static inline u32 pri_tpccs_addr_width(void) | ||
113 | { | ||
114 | return 11; /* from where? */ | ||
115 | } | ||
116 | static inline u32 pri_tpccs_addr_mask(u32 addr) | ||
117 | { | ||
118 | return addr & ((1 << pri_tpccs_addr_width()) - 1); | ||
119 | } | ||
120 | static inline u32 pri_fbpa_addr_mask(struct gk20a *g, u32 addr) | ||
121 | { | ||
122 | return addr & (nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) - 1); | ||
123 | } | ||
124 | static inline u32 pri_tpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc) | ||
125 | { | ||
126 | u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE); | ||
127 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
128 | u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_BASE); | ||
129 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
130 | return gpc_base + (gpc * gpc_stride) + | ||
131 | tpc_in_gpc_base + (tpc * tpc_in_gpc_stride) + | ||
132 | addr; | ||
133 | } | ||
134 | static inline bool pri_is_tpc_addr_shared(struct gk20a *g, u32 addr) | ||
135 | { | ||
136 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
137 | u32 tpc_in_gpc_shared_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_SHARED_BASE); | ||
138 | return (addr >= tpc_in_gpc_shared_base) && | ||
139 | (addr < (tpc_in_gpc_shared_base + | ||
140 | tpc_in_gpc_stride)); | ||
141 | } | ||
142 | static inline u32 pri_fbpa_addr(struct gk20a *g, u32 addr, u32 fbpa) | ||
143 | { | ||
144 | return (nvgpu_get_litter_value(g, GPU_LIT_FBPA_BASE) + addr + | ||
145 | (fbpa * nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE))); | ||
146 | } | ||
147 | static inline bool pri_is_fbpa_addr_shared(struct gk20a *g, u32 addr) | ||
148 | { | ||
149 | u32 fbpa_shared_base = nvgpu_get_litter_value(g, GPU_LIT_FBPA_SHARED_BASE); | ||
150 | u32 fbpa_stride = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE); | ||
151 | return ((addr >= fbpa_shared_base) && | ||
152 | (addr < (fbpa_shared_base + fbpa_stride))); | ||
153 | } | ||
154 | static inline bool pri_is_fbpa_addr(struct gk20a *g, u32 addr) | ||
155 | { | ||
156 | u32 fbpa_base = nvgpu_get_litter_value(g, GPU_LIT_FBPA_BASE); | ||
157 | u32 fbpa_stride = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE); | ||
158 | u32 num_fbpas = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS); | ||
159 | return (((addr >= fbpa_base) && | ||
160 | (addr < (fbpa_base + num_fbpas * fbpa_stride))) | ||
161 | || pri_is_fbpa_addr_shared(g, addr)); | ||
162 | } | ||
163 | /* | ||
164 | * BE pri addressing | ||
165 | */ | ||
166 | static inline u32 pri_becs_addr_width(void) | ||
167 | { | ||
168 | return 10;/* from where? */ | ||
169 | } | ||
170 | static inline u32 pri_becs_addr_mask(u32 addr) | ||
171 | { | ||
172 | return addr & ((1 << pri_becs_addr_width()) - 1); | ||
173 | } | ||
174 | static inline bool pri_is_be_addr_shared(struct gk20a *g, u32 addr) | ||
175 | { | ||
176 | u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_SHARED_BASE); | ||
177 | u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE); | ||
178 | return (addr >= rop_shared_base) && | ||
179 | (addr < rop_shared_base + rop_stride); | ||
180 | } | ||
181 | static inline u32 pri_be_shared_addr(struct gk20a *g, u32 addr) | ||
182 | { | ||
183 | u32 rop_shared_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_SHARED_BASE); | ||
184 | return rop_shared_base + pri_becs_addr_mask(addr); | ||
185 | } | ||
186 | static inline bool pri_is_be_addr(struct gk20a *g, u32 addr) | ||
187 | { | ||
188 | u32 rop_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_BASE); | ||
189 | u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE); | ||
190 | return ((addr >= rop_base) && | ||
191 | (addr < rop_base + g->ltc_count * rop_stride)) || | ||
192 | pri_is_be_addr_shared(g, addr); | ||
193 | } | ||
194 | |||
195 | static inline u32 pri_get_be_num(struct gk20a *g, u32 addr) | ||
196 | { | ||
197 | u32 i, start; | ||
198 | u32 num_fbps = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPS); | ||
199 | u32 rop_base = nvgpu_get_litter_value(g, GPU_LIT_ROP_BASE); | ||
200 | u32 rop_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE); | ||
201 | for (i = 0; i < num_fbps; i++) { | ||
202 | start = rop_base + (i * rop_stride); | ||
203 | if ((addr >= start) && (addr < (start + rop_stride))) | ||
204 | return i; | ||
205 | } | ||
206 | return 0; | ||
207 | } | ||
208 | |||
209 | /* | ||
210 | * PPC pri addressing | ||
211 | */ | ||
212 | static inline u32 pri_ppccs_addr_width(void) | ||
213 | { | ||
214 | return 9; /* from where? */ | ||
215 | } | ||
216 | static inline u32 pri_ppccs_addr_mask(u32 addr) | ||
217 | { | ||
218 | return addr & ((1 << pri_ppccs_addr_width()) - 1); | ||
219 | } | ||
220 | static inline u32 pri_ppc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 ppc) | ||
221 | { | ||
222 | u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE); | ||
223 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
224 | u32 ppc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_BASE); | ||
225 | u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE); | ||
226 | return gpc_base + (gpc * gpc_stride) + | ||
227 | ppc_in_gpc_base + (ppc * ppc_in_gpc_stride) + addr; | ||
228 | } | ||
229 | |||
230 | /* | ||
231 | * LTC pri addressing | ||
232 | */ | ||
233 | static inline bool pri_is_ltc_addr(u32 addr) | ||
234 | { | ||
235 | return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v())); | ||
236 | } | ||
237 | |||
238 | enum ctxsw_addr_type { | ||
239 | CTXSW_ADDR_TYPE_SYS = 0, | ||
240 | CTXSW_ADDR_TYPE_GPC = 1, | ||
241 | CTXSW_ADDR_TYPE_TPC = 2, | ||
242 | CTXSW_ADDR_TYPE_BE = 3, | ||
243 | CTXSW_ADDR_TYPE_PPC = 4, | ||
244 | CTXSW_ADDR_TYPE_LTCS = 5, | ||
245 | CTXSW_ADDR_TYPE_FBPA = 6, | ||
246 | CTXSW_ADDR_TYPE_EGPC = 7, | ||
247 | CTXSW_ADDR_TYPE_ETPC = 8, | ||
248 | }; | ||
249 | |||
250 | #define PRI_BROADCAST_FLAGS_NONE 0 | ||
251 | #define PRI_BROADCAST_FLAGS_GPC BIT(0) | ||
252 | #define PRI_BROADCAST_FLAGS_TPC BIT(1) | ||
253 | #define PRI_BROADCAST_FLAGS_BE BIT(2) | ||
254 | #define PRI_BROADCAST_FLAGS_PPC BIT(3) | ||
255 | #define PRI_BROADCAST_FLAGS_LTCS BIT(4) | ||
256 | #define PRI_BROADCAST_FLAGS_LTSS BIT(5) | ||
257 | #define PRI_BROADCAST_FLAGS_FBPA BIT(6) | ||
258 | #define PRI_BROADCAST_FLAGS_EGPC BIT(7) | ||
259 | #define PRI_BROADCAST_FLAGS_ETPC BIT(8) | ||
260 | |||
261 | #endif /* GR_PRI_GK20A_H */ | ||