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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index e5d7e83b..f43e57fd 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -19,6 +19,7 @@
19#define GR_GK20A_H 19#define GR_GK20A_H
20 20
21#include <linux/slab.h> 21#include <linux/slab.h>
22#include <uapi/linux/nvgpu.h>
22#ifdef CONFIG_ARCH_TEGRA_18x_SOC 23#ifdef CONFIG_ARCH_TEGRA_18x_SOC
23#include "gr_t18x.h" 24#include "gr_t18x.h"
24#endif 25#endif
@@ -29,6 +30,7 @@
29 30
30#include "tsg_gk20a.h" 31#include "tsg_gk20a.h"
31#include "gr_ctx_gk20a.h" 32#include "gr_ctx_gk20a.h"
33#include "mm_gk20a.h"
32 34
33#define GR_IDLE_CHECK_DEFAULT 10 /* usec */ 35#define GR_IDLE_CHECK_DEFAULT 10 /* usec */
34#define GR_IDLE_CHECK_MAX 200 /* usec */ 36#define GR_IDLE_CHECK_MAX 200 /* usec */
@@ -42,6 +44,8 @@
42 44
43#define GK20A_GR_MAX_PES_PER_GPC 3 45#define GK20A_GR_MAX_PES_PER_GPC 3
44 46
47struct channel_gk20a;
48
45enum /* global_ctx_buffer */ { 49enum /* global_ctx_buffer */ {
46 CIRCULAR = 0, 50 CIRCULAR = 0,
47 PAGEPOOL = 1, 51 PAGEPOOL = 1,
@@ -201,6 +205,12 @@ struct gr_gk20a_isr_data {
201 u32 class_num; 205 u32 class_num;
202}; 206};
203 207
208struct gr_ctx_buffer_desc {
209 void (*destroy)(struct gk20a *, struct gr_ctx_buffer_desc *);
210 struct mem_desc mem;
211 void *priv;
212};
213
204struct nvgpu_preemption_modes_rec { 214struct nvgpu_preemption_modes_rec {
205 u32 graphics_preemption_mode_flags; /* supported preemption modes */ 215 u32 graphics_preemption_mode_flags; /* supported preemption modes */
206 u32 compute_preemption_mode_flags; /* supported preemption modes */ 216 u32 compute_preemption_mode_flags; /* supported preemption modes */
@@ -376,6 +386,23 @@ struct gr_gk20a {
376 386
377void gk20a_fecs_dump_falcon_stats(struct gk20a *g); 387void gk20a_fecs_dump_falcon_stats(struct gk20a *g);
378 388
389struct gr_ctx_desc {
390 struct mem_desc mem;
391
392 u32 graphics_preempt_mode;
393 u32 compute_preempt_mode;
394#ifdef CONFIG_ARCH_TEGRA_18x_SOC
395 struct gr_ctx_desc_t18x t18x;
396#endif
397#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
398 u64 virt_ctx;
399#endif
400};
401
402struct ctx_header_desc {
403 struct mem_desc mem;
404};
405
379struct gk20a_ctxsw_ucode_segment { 406struct gk20a_ctxsw_ucode_segment {
380 u32 offset; 407 u32 offset;
381 u32 size; 408 u32 size;
@@ -665,6 +692,8 @@ u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr);
665int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, 692int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms,
666 u32 expect_delay); 693 u32 expect_delay);
667 694
695struct dbg_session_gk20a;
696
668bool gr_gk20a_suspend_context(struct channel_gk20a *ch); 697bool gr_gk20a_suspend_context(struct channel_gk20a *ch);
669bool gr_gk20a_resume_context(struct channel_gk20a *ch); 698bool gr_gk20a_resume_context(struct channel_gk20a *ch);
670int gr_gk20a_suspend_contexts(struct gk20a *g, 699int gr_gk20a_suspend_contexts(struct gk20a *g,