diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 779 |
1 files changed, 779 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h new file mode 100644 index 00000000..3377df5d --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -0,0 +1,779 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Engine | ||
3 | * | ||
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef GR_GK20A_H | ||
25 | #define GR_GK20A_H | ||
26 | |||
27 | #include <uapi/linux/nvgpu.h> | ||
28 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
29 | #include "gr_t18x.h" | ||
30 | #endif | ||
31 | #ifdef CONFIG_TEGRA_19x_GPU | ||
32 | #include "gr_t19x.h" | ||
33 | #endif | ||
34 | |||
35 | #include "tsg_gk20a.h" | ||
36 | #include "gr_ctx_gk20a.h" | ||
37 | #include "mm_gk20a.h" | ||
38 | |||
39 | #include <nvgpu/comptags.h> | ||
40 | |||
41 | #define GR_IDLE_CHECK_DEFAULT 10 /* usec */ | ||
42 | #define GR_IDLE_CHECK_MAX 200 /* usec */ | ||
43 | #define GR_FECS_POLL_INTERVAL 5 /* usec */ | ||
44 | |||
45 | #define INVALID_SCREEN_TILE_ROW_OFFSET 0xFFFFFFFF | ||
46 | #define INVALID_MAX_WAYS 0xFFFFFFFF | ||
47 | |||
48 | #define GK20A_FECS_UCODE_IMAGE "fecs.bin" | ||
49 | #define GK20A_GPCCS_UCODE_IMAGE "gpccs.bin" | ||
50 | |||
51 | #define GK20A_GR_MAX_PES_PER_GPC 3 | ||
52 | |||
53 | #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ | ||
54 | |||
55 | /* | ||
56 | * allocate a minimum of 1 page (4KB) worth of patch space, this is 512 entries | ||
57 | * of address and data pairs | ||
58 | */ | ||
59 | #define PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY 2 | ||
60 | #define PATCH_CTX_SLOTS_PER_PAGE \ | ||
61 | (PAGE_SIZE/(PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY * sizeof(u32))) | ||
62 | #define PATCH_CTX_ENTRIES_FROM_SIZE(size) (size/sizeof(u32)) | ||
63 | |||
64 | #define NVGPU_PREEMPTION_MODE_GRAPHICS_WFI (1 << 0) | ||
65 | #define NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP (1 << 1) | ||
66 | |||
67 | #define NVGPU_PREEMPTION_MODE_COMPUTE_WFI (1 << 0) | ||
68 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CTA (1 << 1) | ||
69 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CILP (1 << 2) | ||
70 | |||
71 | struct channel_gk20a; | ||
72 | struct nvgpu_warpstate; | ||
73 | |||
74 | enum /* global_ctx_buffer */ { | ||
75 | CIRCULAR = 0, | ||
76 | PAGEPOOL = 1, | ||
77 | ATTRIBUTE = 2, | ||
78 | CIRCULAR_VPR = 3, | ||
79 | PAGEPOOL_VPR = 4, | ||
80 | ATTRIBUTE_VPR = 5, | ||
81 | GOLDEN_CTX = 6, | ||
82 | PRIV_ACCESS_MAP = 7, | ||
83 | NR_GLOBAL_CTX_BUF = 8 | ||
84 | }; | ||
85 | |||
86 | /* either ATTRIBUTE or ATTRIBUTE_VPR maps to ATTRIBUTE_VA */ | ||
87 | enum /*global_ctx_buffer_va */ { | ||
88 | CIRCULAR_VA = 0, | ||
89 | PAGEPOOL_VA = 1, | ||
90 | ATTRIBUTE_VA = 2, | ||
91 | GOLDEN_CTX_VA = 3, | ||
92 | PRIV_ACCESS_MAP_VA = 4, | ||
93 | NR_GLOBAL_CTX_BUF_VA = 5 | ||
94 | }; | ||
95 | |||
96 | enum { | ||
97 | WAIT_UCODE_LOOP, | ||
98 | WAIT_UCODE_TIMEOUT, | ||
99 | WAIT_UCODE_ERROR, | ||
100 | WAIT_UCODE_OK | ||
101 | }; | ||
102 | |||
103 | enum { | ||
104 | GR_IS_UCODE_OP_EQUAL, | ||
105 | GR_IS_UCODE_OP_NOT_EQUAL, | ||
106 | GR_IS_UCODE_OP_AND, | ||
107 | GR_IS_UCODE_OP_LESSER, | ||
108 | GR_IS_UCODE_OP_LESSER_EQUAL, | ||
109 | GR_IS_UCODE_OP_SKIP | ||
110 | }; | ||
111 | |||
112 | enum { | ||
113 | eUcodeHandshakeInitComplete = 1, | ||
114 | eUcodeHandshakeMethodFinished | ||
115 | }; | ||
116 | |||
117 | enum { | ||
118 | ELCG_MODE = (1 << 0), | ||
119 | BLCG_MODE = (1 << 1), | ||
120 | INVALID_MODE = (1 << 2) | ||
121 | }; | ||
122 | |||
123 | enum { | ||
124 | ELCG_RUN, /* clk always run, i.e. disable elcg */ | ||
125 | ELCG_STOP, /* clk is stopped */ | ||
126 | ELCG_AUTO /* clk will run when non-idle, standard elcg mode */ | ||
127 | }; | ||
128 | |||
129 | enum { | ||
130 | BLCG_RUN, /* clk always run, i.e. disable blcg */ | ||
131 | BLCG_AUTO /* clk will run when non-idle, standard blcg mode */ | ||
132 | }; | ||
133 | |||
134 | enum { | ||
135 | NVGPU_EVENT_ID_BPT_INT = 0, | ||
136 | NVGPU_EVENT_ID_BPT_PAUSE, | ||
137 | NVGPU_EVENT_ID_BLOCKING_SYNC, | ||
138 | NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED, | ||
139 | NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE, | ||
140 | NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN, | ||
141 | NVGPU_EVENT_ID_MAX, | ||
142 | }; | ||
143 | |||
144 | #ifndef GR_GO_IDLE_BUNDLE | ||
145 | #define GR_GO_IDLE_BUNDLE 0x0000e100 /* --V-B */ | ||
146 | #endif | ||
147 | |||
148 | struct gr_channel_map_tlb_entry { | ||
149 | u32 curr_ctx; | ||
150 | u32 chid; | ||
151 | u32 tsgid; | ||
152 | }; | ||
153 | |||
154 | struct gr_zcull_gk20a { | ||
155 | u32 aliquot_width; | ||
156 | u32 aliquot_height; | ||
157 | u32 aliquot_size; | ||
158 | u32 total_aliquots; | ||
159 | |||
160 | u32 width_align_pixels; | ||
161 | u32 height_align_pixels; | ||
162 | u32 pixel_squares_by_aliquots; | ||
163 | }; | ||
164 | |||
165 | struct gr_zcull_info { | ||
166 | u32 width_align_pixels; | ||
167 | u32 height_align_pixels; | ||
168 | u32 pixel_squares_by_aliquots; | ||
169 | u32 aliquot_total; | ||
170 | u32 region_byte_multiplier; | ||
171 | u32 region_header_size; | ||
172 | u32 subregion_header_size; | ||
173 | u32 subregion_width_align_pixels; | ||
174 | u32 subregion_height_align_pixels; | ||
175 | u32 subregion_count; | ||
176 | }; | ||
177 | |||
178 | #define GK20A_ZBC_COLOR_VALUE_SIZE 4 /* RGBA */ | ||
179 | |||
180 | #define GK20A_STARTOF_ZBC_TABLE 1 /* index zero reserved to indicate "not ZBCd" */ | ||
181 | #define GK20A_SIZEOF_ZBC_TABLE 16 /* match ltcs_ltss_dstg_zbc_index_address width (4) */ | ||
182 | #define GK20A_ZBC_TABLE_SIZE (16 - 1) | ||
183 | |||
184 | #define GK20A_ZBC_TYPE_INVALID 0 | ||
185 | #define GK20A_ZBC_TYPE_COLOR 1 | ||
186 | #define GK20A_ZBC_TYPE_DEPTH 2 | ||
187 | #define T19X_ZBC 3 | ||
188 | |||
189 | struct zbc_color_table { | ||
190 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; | ||
191 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; | ||
192 | u32 format; | ||
193 | u32 ref_cnt; | ||
194 | }; | ||
195 | |||
196 | struct zbc_depth_table { | ||
197 | u32 depth; | ||
198 | u32 format; | ||
199 | u32 ref_cnt; | ||
200 | }; | ||
201 | |||
202 | struct zbc_entry { | ||
203 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; | ||
204 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; | ||
205 | u32 depth; | ||
206 | u32 type; /* color or depth */ | ||
207 | u32 format; | ||
208 | }; | ||
209 | |||
210 | struct zbc_query_params { | ||
211 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; | ||
212 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; | ||
213 | u32 depth; | ||
214 | u32 ref_cnt; | ||
215 | u32 format; | ||
216 | u32 type; /* color or depth */ | ||
217 | u32 index_size; /* [out] size, [in] index */ | ||
218 | }; | ||
219 | |||
220 | struct sm_info { | ||
221 | u32 gpc_index; | ||
222 | u32 tpc_index; | ||
223 | u32 sm_index; | ||
224 | u32 global_tpc_index; | ||
225 | }; | ||
226 | |||
227 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
228 | struct gk20a_cs_snapshot_client; | ||
229 | struct gk20a_cs_snapshot; | ||
230 | #endif | ||
231 | |||
232 | struct gr_gk20a_isr_data { | ||
233 | u32 addr; | ||
234 | u32 data_lo; | ||
235 | u32 data_hi; | ||
236 | u32 curr_ctx; | ||
237 | u32 chid; | ||
238 | u32 offset; | ||
239 | u32 sub_chan; | ||
240 | u32 class_num; | ||
241 | }; | ||
242 | |||
243 | struct gr_ctx_buffer_desc { | ||
244 | void (*destroy)(struct gk20a *, struct gr_ctx_buffer_desc *); | ||
245 | struct nvgpu_mem mem; | ||
246 | void *priv; | ||
247 | }; | ||
248 | |||
249 | struct nvgpu_preemption_modes_rec { | ||
250 | u32 graphics_preemption_mode_flags; /* supported preemption modes */ | ||
251 | u32 compute_preemption_mode_flags; /* supported preemption modes */ | ||
252 | |||
253 | u32 default_graphics_preempt_mode; /* default mode */ | ||
254 | u32 default_compute_preempt_mode; /* default mode */ | ||
255 | }; | ||
256 | |||
257 | struct nvgpu_gr_sm_error_state { | ||
258 | u32 hww_global_esr; | ||
259 | u32 hww_warp_esr; | ||
260 | u64 hww_warp_esr_pc; | ||
261 | u32 hww_global_esr_report_mask; | ||
262 | u32 hww_warp_esr_report_mask; | ||
263 | }; | ||
264 | |||
265 | struct gr_gk20a { | ||
266 | struct gk20a *g; | ||
267 | struct { | ||
268 | bool dynamic; | ||
269 | |||
270 | u32 buffer_size; | ||
271 | u32 buffer_total_size; | ||
272 | |||
273 | bool golden_image_initialized; | ||
274 | u32 golden_image_size; | ||
275 | u32 *local_golden_image; | ||
276 | |||
277 | u32 hwpm_ctxsw_buffer_offset_map_count; | ||
278 | struct ctxsw_buf_offset_map_entry *hwpm_ctxsw_buffer_offset_map; | ||
279 | |||
280 | u32 zcull_ctxsw_image_size; | ||
281 | |||
282 | u32 pm_ctxsw_image_size; | ||
283 | |||
284 | u32 buffer_header_size; | ||
285 | |||
286 | u32 priv_access_map_size; | ||
287 | |||
288 | struct gr_ucode_gk20a ucode; | ||
289 | |||
290 | struct av_list_gk20a sw_bundle_init; | ||
291 | struct av_list_gk20a sw_method_init; | ||
292 | struct aiv_list_gk20a sw_ctx_load; | ||
293 | struct av_list_gk20a sw_non_ctx_load; | ||
294 | struct av_list_gk20a sw_veid_bundle_init; | ||
295 | struct { | ||
296 | struct aiv_list_gk20a sys; | ||
297 | struct aiv_list_gk20a gpc; | ||
298 | struct aiv_list_gk20a tpc; | ||
299 | struct aiv_list_gk20a zcull_gpc; | ||
300 | struct aiv_list_gk20a ppc; | ||
301 | struct aiv_list_gk20a pm_sys; | ||
302 | struct aiv_list_gk20a pm_gpc; | ||
303 | struct aiv_list_gk20a pm_tpc; | ||
304 | struct aiv_list_gk20a pm_ppc; | ||
305 | struct aiv_list_gk20a perf_sys; | ||
306 | struct aiv_list_gk20a perf_gpc; | ||
307 | struct aiv_list_gk20a fbp; | ||
308 | struct aiv_list_gk20a fbp_router; | ||
309 | struct aiv_list_gk20a gpc_router; | ||
310 | struct aiv_list_gk20a pm_ltc; | ||
311 | struct aiv_list_gk20a pm_fbpa; | ||
312 | struct aiv_list_gk20a perf_sys_router; | ||
313 | struct aiv_list_gk20a perf_pma; | ||
314 | struct aiv_list_gk20a pm_rop; | ||
315 | struct aiv_list_gk20a pm_ucgpc; | ||
316 | struct aiv_list_gk20a etpc; | ||
317 | } ctxsw_regs; | ||
318 | int regs_base_index; | ||
319 | bool valid; | ||
320 | } ctx_vars; | ||
321 | |||
322 | struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */ | ||
323 | struct nvgpu_mutex fecs_mutex; /* protect fecs method */ | ||
324 | |||
325 | #define GR_NETLIST_DYNAMIC -1 | ||
326 | #define GR_NETLIST_STATIC_A 'A' | ||
327 | int netlist; | ||
328 | |||
329 | struct nvgpu_cond init_wq; | ||
330 | int initialized; | ||
331 | |||
332 | u32 num_fbps; | ||
333 | |||
334 | u32 comptags_per_cacheline; | ||
335 | u32 slices_per_ltc; | ||
336 | u32 cacheline_size; | ||
337 | u32 gobs_per_comptagline_per_slice; | ||
338 | |||
339 | u32 max_gpc_count; | ||
340 | u32 max_fbps_count; | ||
341 | u32 max_tpc_per_gpc_count; | ||
342 | u32 max_zcull_per_gpc_count; | ||
343 | u32 max_tpc_count; | ||
344 | |||
345 | u32 sys_count; | ||
346 | u32 gpc_count; | ||
347 | u32 pe_count_per_gpc; | ||
348 | u32 ppc_count; | ||
349 | u32 *gpc_ppc_count; | ||
350 | u32 tpc_count; | ||
351 | u32 *gpc_tpc_count; | ||
352 | u32 *gpc_tpc_mask; | ||
353 | u32 zcb_count; | ||
354 | u32 *gpc_zcb_count; | ||
355 | u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC]; | ||
356 | u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC]; | ||
357 | u32 *gpc_skip_mask; | ||
358 | |||
359 | u32 bundle_cb_default_size; | ||
360 | u32 min_gpm_fifo_depth; | ||
361 | u32 bundle_cb_token_limit; | ||
362 | u32 attrib_cb_default_size; | ||
363 | u32 attrib_cb_size; | ||
364 | u32 alpha_cb_default_size; | ||
365 | u32 alpha_cb_size; | ||
366 | u32 timeslice_mode; | ||
367 | u32 czf_bypass; | ||
368 | u32 pd_max_batches; | ||
369 | u32 gfxp_wfi_timeout_count; | ||
370 | |||
371 | struct gr_ctx_buffer_desc global_ctx_buffer[NR_GLOBAL_CTX_BUF]; | ||
372 | |||
373 | struct nvgpu_mem mmu_wr_mem; | ||
374 | struct nvgpu_mem mmu_rd_mem; | ||
375 | |||
376 | u8 *map_tiles; | ||
377 | u32 map_tile_count; | ||
378 | u32 map_row_offset; | ||
379 | |||
380 | u32 max_comptag_mem; /* max memory size (MB) for comptag */ | ||
381 | struct compbit_store_desc compbit_store; | ||
382 | struct gk20a_comptag_allocator comp_tags; | ||
383 | |||
384 | struct gr_zcull_gk20a zcull; | ||
385 | |||
386 | struct nvgpu_mutex zbc_lock; | ||
387 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; | ||
388 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; | ||
389 | #ifdef CONFIG_TEGRA_19x_GPU | ||
390 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; | ||
391 | #endif | ||
392 | s32 max_default_color_index; | ||
393 | s32 max_default_depth_index; | ||
394 | #ifdef CONFIG_TEGRA_19x_GPU | ||
395 | s32 max_default_s_index; | ||
396 | #endif | ||
397 | |||
398 | u32 max_used_color_index; | ||
399 | u32 max_used_depth_index; | ||
400 | #ifdef CONFIG_TEGRA_19x_GPU | ||
401 | u32 max_used_s_index; | ||
402 | #endif | ||
403 | |||
404 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ | ||
405 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; | ||
406 | u32 channel_tlb_flush_index; | ||
407 | struct nvgpu_spinlock ch_tlb_lock; | ||
408 | |||
409 | void (*remove_support)(struct gr_gk20a *gr); | ||
410 | bool sw_ready; | ||
411 | bool skip_ucode_init; | ||
412 | |||
413 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
414 | struct gr_t18x t18x; | ||
415 | #endif | ||
416 | |||
417 | u32 fbp_en_mask; | ||
418 | u32 *fbp_rop_l2_en_mask; | ||
419 | u32 no_of_sm; | ||
420 | struct sm_info *sm_to_cluster; | ||
421 | struct nvgpu_gr_sm_error_state *sm_error_states; | ||
422 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
423 | struct nvgpu_mutex cs_lock; | ||
424 | struct gk20a_cs_snapshot *cs_data; | ||
425 | #endif | ||
426 | u32 max_css_buffer_size; | ||
427 | }; | ||
428 | |||
429 | void gk20a_fecs_dump_falcon_stats(struct gk20a *g); | ||
430 | |||
431 | struct gr_ctx_desc { | ||
432 | struct nvgpu_mem mem; | ||
433 | |||
434 | u32 graphics_preempt_mode; | ||
435 | u32 compute_preempt_mode; | ||
436 | bool boosted_ctx; | ||
437 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
438 | struct gr_ctx_desc_t18x t18x; | ||
439 | #endif | ||
440 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | ||
441 | u64 virt_ctx; | ||
442 | #endif | ||
443 | }; | ||
444 | |||
445 | struct ctx_header_desc { | ||
446 | struct nvgpu_mem mem; | ||
447 | }; | ||
448 | |||
449 | struct gk20a_ctxsw_ucode_segment { | ||
450 | u32 offset; | ||
451 | u32 size; | ||
452 | }; | ||
453 | |||
454 | struct gk20a_ctxsw_ucode_segments { | ||
455 | u32 boot_entry; | ||
456 | u32 boot_imem_offset; | ||
457 | u32 boot_signature; | ||
458 | struct gk20a_ctxsw_ucode_segment boot; | ||
459 | struct gk20a_ctxsw_ucode_segment code; | ||
460 | struct gk20a_ctxsw_ucode_segment data; | ||
461 | }; | ||
462 | |||
463 | /* sums over the ucode files as sequences of u32, computed to the | ||
464 | * boot_signature field in the structure above */ | ||
465 | |||
466 | /* T18X FECS remains same as T21X, | ||
467 | * so FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED used | ||
468 | * for T18X*/ | ||
469 | #define FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED 0x68edab34 | ||
470 | #define FALCON_UCODE_SIG_T21X_FECS_WITH_DMEM_SIZE 0x9121ab5c | ||
471 | #define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5c | ||
472 | #define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78 | ||
473 | #define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b | ||
474 | #define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09f | ||
475 | |||
476 | #define FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED 0x3d3d65e2 | ||
477 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5 | ||
478 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3 | ||
479 | #define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877 | ||
480 | |||
481 | #define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED 0x93671b7d | ||
482 | #define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED2 0x4d6cbc10 | ||
483 | |||
484 | #define FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED 0x393161da | ||
485 | |||
486 | struct gk20a_ctxsw_ucode_info { | ||
487 | u64 *p_va; | ||
488 | struct nvgpu_mem inst_blk_desc; | ||
489 | struct nvgpu_mem surface_desc; | ||
490 | struct gk20a_ctxsw_ucode_segments fecs; | ||
491 | struct gk20a_ctxsw_ucode_segments gpccs; | ||
492 | }; | ||
493 | |||
494 | struct gk20a_ctxsw_bootloader_desc { | ||
495 | u32 start_offset; | ||
496 | u32 size; | ||
497 | u32 imem_offset; | ||
498 | u32 entry_point; | ||
499 | }; | ||
500 | |||
501 | struct fecs_method_op_gk20a { | ||
502 | struct { | ||
503 | u32 addr; | ||
504 | u32 data; | ||
505 | } method; | ||
506 | |||
507 | struct { | ||
508 | u32 id; | ||
509 | u32 data; | ||
510 | u32 clr; | ||
511 | u32 *ret; | ||
512 | u32 ok; | ||
513 | u32 fail; | ||
514 | } mailbox; | ||
515 | |||
516 | struct { | ||
517 | u32 ok; | ||
518 | u32 fail; | ||
519 | } cond; | ||
520 | |||
521 | }; | ||
522 | |||
523 | struct nvgpu_warpstate { | ||
524 | u64 valid_warps[2]; | ||
525 | u64 trapped_warps[2]; | ||
526 | u64 paused_warps[2]; | ||
527 | }; | ||
528 | |||
529 | struct gpu_ops; | ||
530 | int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | ||
531 | struct channel_gk20a *c); | ||
532 | void gk20a_init_gr(struct gk20a *g); | ||
533 | int gk20a_init_gr_support(struct gk20a *g); | ||
534 | int gk20a_enable_gr_hw(struct gk20a *g); | ||
535 | int gk20a_gr_reset(struct gk20a *g); | ||
536 | void gk20a_gr_wait_initialized(struct gk20a *g); | ||
537 | |||
538 | int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a); | ||
539 | |||
540 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); | ||
541 | |||
542 | int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags); | ||
543 | void gk20a_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); | ||
544 | |||
545 | int gk20a_gr_isr(struct gk20a *g); | ||
546 | int gk20a_gr_nonstall_isr(struct gk20a *g); | ||
547 | |||
548 | /* zcull */ | ||
549 | u32 gr_gk20a_get_ctxsw_zcull_size(struct gk20a *g, struct gr_gk20a *gr); | ||
550 | int gr_gk20a_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, | ||
551 | struct channel_gk20a *c, u64 zcull_va, u32 mode); | ||
552 | int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | ||
553 | struct gr_zcull_info *zcull_params); | ||
554 | void gr_gk20a_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, | ||
555 | u32 *zcull_map_tiles); | ||
556 | /* zbc */ | ||
557 | int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
558 | struct zbc_entry *zbc_val); | ||
559 | int gr_gk20a_query_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
560 | struct zbc_query_params *query_params); | ||
561 | int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | ||
562 | struct zbc_entry *zbc_val); | ||
563 | int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr); | ||
564 | |||
565 | /* pmu */ | ||
566 | int gr_gk20a_fecs_get_reglist_img_size(struct gk20a *g, u32 *size); | ||
567 | int gr_gk20a_fecs_set_reglist_bind_inst(struct gk20a *g, | ||
568 | struct nvgpu_mem *inst_block); | ||
569 | int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); | ||
570 | |||
571 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); | ||
572 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine); | ||
573 | |||
574 | void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config); | ||
575 | |||
576 | /* sm */ | ||
577 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); | ||
578 | u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); | ||
579 | |||
580 | #define gr_gk20a_elpg_protected_call(g, func) \ | ||
581 | ({ \ | ||
582 | int err = 0; \ | ||
583 | if (g->support_pmu && g->elpg_enabled) {\ | ||
584 | err = nvgpu_pmu_disable_elpg(g); \ | ||
585 | if (err) \ | ||
586 | nvgpu_pmu_enable_elpg(g); \ | ||
587 | } \ | ||
588 | if (!err) { \ | ||
589 | err = func; \ | ||
590 | if (g->support_pmu && g->elpg_enabled) \ | ||
591 | nvgpu_pmu_enable_elpg(g); \ | ||
592 | } \ | ||
593 | err; \ | ||
594 | }) | ||
595 | |||
596 | int gk20a_gr_suspend(struct gk20a *g); | ||
597 | |||
598 | struct nvgpu_dbg_gpu_reg_op; | ||
599 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | ||
600 | struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, | ||
601 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops); | ||
602 | int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | ||
603 | struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, | ||
604 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, | ||
605 | bool ch_is_curr_ctx); | ||
606 | int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g, | ||
607 | u32 addr, | ||
608 | u32 max_offsets, | ||
609 | u32 *offsets, u32 *offset_addrs, | ||
610 | u32 *num_offsets, | ||
611 | bool is_quad, u32 quad); | ||
612 | int gr_gk20a_get_pm_ctx_buffer_offsets(struct gk20a *g, | ||
613 | u32 addr, | ||
614 | u32 max_offsets, | ||
615 | u32 *offsets, u32 *offset_addrs, | ||
616 | u32 *num_offsets); | ||
617 | int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, | ||
618 | struct channel_gk20a *c, | ||
619 | bool enable_smpc_ctxsw); | ||
620 | int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | ||
621 | struct channel_gk20a *c, | ||
622 | bool enable_hwpm_ctxsw); | ||
623 | |||
624 | struct channel_ctx_gk20a; | ||
625 | void gr_gk20a_ctx_patch_write(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, | ||
626 | u32 addr, u32 data, bool patch); | ||
627 | int gr_gk20a_ctx_patch_write_begin(struct gk20a *g, | ||
628 | struct channel_ctx_gk20a *ch_ctx, | ||
629 | bool update_patch_count); | ||
630 | void gr_gk20a_ctx_patch_write_end(struct gk20a *g, | ||
631 | struct channel_ctx_gk20a *ch_ctx, | ||
632 | bool update_patch_count); | ||
633 | void gr_gk20a_commit_global_pagepool(struct gk20a *g, | ||
634 | struct channel_ctx_gk20a *ch_ctx, | ||
635 | u64 addr, u32 size, bool patch); | ||
636 | void gk20a_gr_set_shader_exceptions(struct gk20a *g, u32 data); | ||
637 | void gr_gk20a_enable_hww_exceptions(struct gk20a *g); | ||
638 | int gr_gk20a_init_fs_state(struct gk20a *g); | ||
639 | int gr_gk20a_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr); | ||
640 | int gr_gk20a_init_ctxsw_ucode(struct gk20a *g); | ||
641 | int gr_gk20a_load_ctxsw_ucode(struct gk20a *g); | ||
642 | void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g); | ||
643 | void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base, | ||
644 | struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset); | ||
645 | void gr_gk20a_load_ctxsw_ucode_boot(struct gk20a *g, u64 addr_base, | ||
646 | struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset); | ||
647 | |||
648 | |||
649 | void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c); | ||
650 | int gr_gk20a_disable_ctxsw(struct gk20a *g); | ||
651 | int gr_gk20a_enable_ctxsw(struct gk20a *g); | ||
652 | void gk20a_gr_resume_single_sm(struct gk20a *g, | ||
653 | u32 gpc, u32 tpc, u32 sm); | ||
654 | void gk20a_gr_resume_all_sms(struct gk20a *g); | ||
655 | void gk20a_gr_suspend_single_sm(struct gk20a *g, | ||
656 | u32 gpc, u32 tpc, u32 sm, | ||
657 | u32 global_esr_mask, bool check_errors); | ||
658 | void gk20a_gr_suspend_all_sms(struct gk20a *g, | ||
659 | u32 global_esr_mask, bool check_errors); | ||
660 | u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index); | ||
661 | int gr_gk20a_set_sm_debug_mode(struct gk20a *g, | ||
662 | struct channel_gk20a *ch, u64 sms, bool enable); | ||
663 | bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch); | ||
664 | int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | ||
665 | struct zbc_entry *color_val, u32 index); | ||
666 | int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | ||
667 | struct zbc_entry *depth_val, u32 index); | ||
668 | int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | ||
669 | struct zbc_entry *zbc_val); | ||
670 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); | ||
671 | int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms, | ||
672 | u32 expect_delay); | ||
673 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | ||
674 | bool *post_event, struct channel_gk20a *fault_ch, | ||
675 | u32 *hww_global_esr); | ||
676 | int gr_gk20a_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
677 | bool *post_event); | ||
678 | int gr_gk20a_init_ctx_state(struct gk20a *g); | ||
679 | int gr_gk20a_submit_fecs_method_op(struct gk20a *g, | ||
680 | struct fecs_method_op_gk20a op, | ||
681 | bool sleepduringwait); | ||
682 | int gr_gk20a_submit_fecs_sideband_method_op(struct gk20a *g, | ||
683 | struct fecs_method_op_gk20a op); | ||
684 | int gr_gk20a_alloc_gr_ctx(struct gk20a *g, | ||
685 | struct gr_ctx_desc **__gr_ctx, struct vm_gk20a *vm, | ||
686 | u32 class, u32 padding); | ||
687 | void gr_gk20a_free_gr_ctx(struct gk20a *g, | ||
688 | struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx); | ||
689 | int gr_gk20a_halt_pipe(struct gk20a *g); | ||
690 | |||
691 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
692 | int gr_gk20a_css_attach(struct channel_gk20a *ch, /* in - main hw structure */ | ||
693 | u32 dmabuf_fd, /* in - dma mapped memory */ | ||
694 | u32 perfmon_id_count, /* in - number of perfmons*/ | ||
695 | u32 *perfmon_id_start, /* out- index of first pm */ | ||
696 | /* out - pointer to client data used in later */ | ||
697 | struct gk20a_cs_snapshot_client **css_client); | ||
698 | |||
699 | int gr_gk20a_css_detach(struct channel_gk20a *ch, | ||
700 | struct gk20a_cs_snapshot_client *css_client); | ||
701 | int gr_gk20a_css_flush(struct channel_gk20a *ch, | ||
702 | struct gk20a_cs_snapshot_client *css_client); | ||
703 | |||
704 | void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g); | ||
705 | |||
706 | #else | ||
707 | /* fake empty cleanup function if no cyclestats snapshots enabled */ | ||
708 | static inline void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g) | ||
709 | { | ||
710 | (void)g; | ||
711 | } | ||
712 | #endif | ||
713 | |||
714 | |||
715 | int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | ||
716 | struct gr_gk20a_isr_data *isr_data); | ||
717 | int gk20a_gr_lock_down_sm(struct gk20a *g, | ||
718 | u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, | ||
719 | bool check_errors); | ||
720 | int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | ||
721 | u32 global_esr_mask, bool check_errors); | ||
722 | int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, | ||
723 | u32 *mailbox_ret, u32 opc_success, | ||
724 | u32 mailbox_ok, u32 opc_fail, | ||
725 | u32 mailbox_fail, bool sleepduringwait); | ||
726 | |||
727 | int gr_gk20a_get_ctx_id(struct gk20a *g, | ||
728 | struct channel_gk20a *c, | ||
729 | u32 *ctx_id); | ||
730 | |||
731 | u32 gk20a_gr_get_sm_hww_warp_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm); | ||
732 | u32 gk20a_gr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm); | ||
733 | |||
734 | int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, | ||
735 | u32 expect_delay); | ||
736 | |||
737 | struct dbg_session_gk20a; | ||
738 | |||
739 | bool gr_gk20a_suspend_context(struct channel_gk20a *ch); | ||
740 | bool gr_gk20a_resume_context(struct channel_gk20a *ch); | ||
741 | int gr_gk20a_suspend_contexts(struct gk20a *g, | ||
742 | struct dbg_session_gk20a *dbg_s, | ||
743 | int *ctx_resident_ch_fd); | ||
744 | int gr_gk20a_resume_contexts(struct gk20a *g, | ||
745 | struct dbg_session_gk20a *dbg_s, | ||
746 | int *ctx_resident_ch_fd); | ||
747 | void gk20a_gr_enable_gpc_exceptions(struct gk20a *g); | ||
748 | void gk20a_gr_enable_exceptions(struct gk20a *g); | ||
749 | int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch); | ||
750 | int gr_gk20a_trigger_suspend(struct gk20a *g); | ||
751 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state); | ||
752 | int gr_gk20a_resume_from_pause(struct gk20a *g); | ||
753 | int gr_gk20a_clear_sm_errors(struct gk20a *g); | ||
754 | u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g); | ||
755 | |||
756 | int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); | ||
757 | |||
758 | void gr_gk20a_init_sm_id_table(struct gk20a *g); | ||
759 | |||
760 | int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); | ||
761 | |||
762 | void gr_gk20a_write_zcull_ptr(struct gk20a *g, | ||
763 | struct nvgpu_mem *mem, u64 gpu_va); | ||
764 | |||
765 | void gr_gk20a_write_pm_ptr(struct gk20a *g, | ||
766 | struct nvgpu_mem *mem, u64 gpu_va); | ||
767 | |||
768 | u32 gk20a_gr_gpc_offset(struct gk20a *g, u32 gpc); | ||
769 | u32 gk20a_gr_tpc_offset(struct gk20a *g, u32 tpc); | ||
770 | void gk20a_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | ||
771 | u32 *esr_sm_sel); | ||
772 | void gk20a_gr_init_ovr_sm_dsm_perf(void); | ||
773 | void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, | ||
774 | u32 **ovr_perf_regs); | ||
775 | void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, | ||
776 | struct nvgpu_mem *mem); | ||
777 | u32 gr_gk20a_get_patch_slots(struct gk20a *g); | ||
778 | |||
779 | #endif /*__GR_GK20A_H__*/ | ||