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path: root/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index e09cfbfa..7db6bccf 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -295,11 +295,28 @@ struct gk20a_ctxsw_ucode_segment {
295struct gk20a_ctxsw_ucode_segments { 295struct gk20a_ctxsw_ucode_segments {
296 u32 boot_entry; 296 u32 boot_entry;
297 u32 boot_imem_offset; 297 u32 boot_imem_offset;
298 u32 boot_signature;
298 struct gk20a_ctxsw_ucode_segment boot; 299 struct gk20a_ctxsw_ucode_segment boot;
299 struct gk20a_ctxsw_ucode_segment code; 300 struct gk20a_ctxsw_ucode_segment code;
300 struct gk20a_ctxsw_ucode_segment data; 301 struct gk20a_ctxsw_ucode_segment data;
301}; 302};
302 303
304/* sums over the ucode files as sequences of u32, computed to the
305 * boot_signature field in the structure above */
306
307#define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78
308#define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b
309#define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09f
310
311#define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5
312#define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3
313#define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877
314
315#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED 0x93671b7d
316#define FALCON_UCODE_SIG_T21X_FECS_WITHOUT_RESERVED2 0x4d6cbc10
317
318#define FALCON_UCODE_SIG_T21X_GPCCS_WITHOUT_RESERVED 0x393161da
319
303struct gk20a_ctxsw_ucode_info { 320struct gk20a_ctxsw_ucode_info {
304 u64 *p_va; 321 u64 *p_va;
305 struct inst_desc inst_blk_desc; 322 struct inst_desc inst_blk_desc;
@@ -422,6 +439,11 @@ int gr_gk20a_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr);
422int gr_gk20a_init_ctxsw_ucode(struct gk20a *g); 439int gr_gk20a_init_ctxsw_ucode(struct gk20a *g);
423int gr_gk20a_load_ctxsw_ucode(struct gk20a *g); 440int gr_gk20a_load_ctxsw_ucode(struct gk20a *g);
424void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g); 441void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g);
442void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base,
443 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
444void gr_gk20a_load_ctxsw_ucode_boot(struct gk20a *g, u64 addr_base,
445 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
446
425 447
426void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c); 448void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c);
427#endif /* GR_GK20A_H */ 449#endif /* GR_GK20A_H */