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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c42
1 files changed, 32 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 636d5714..7bcf5281 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -541,17 +541,12 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
541 return 0; 541 return 0;
542} 542}
543 543
544/* The following is a less brittle way to call gr_gk20a_submit_fecs_method(...) 544int gr_gk20a_submit_fecs_method_op_locked(struct gk20a *g,
545 * We should replace most, if not all, fecs method calls to this instead. */
546int gr_gk20a_submit_fecs_method_op(struct gk20a *g,
547 struct fecs_method_op_gk20a op, 545 struct fecs_method_op_gk20a op,
548 bool sleepduringwait) 546 bool sleepduringwait)
549{ 547{
550 struct gr_gk20a *gr = &g->gr;
551 int ret; 548 int ret;
552 549
553 nvgpu_mutex_acquire(&gr->fecs_mutex);
554
555 if (op.mailbox.id != 0) { 550 if (op.mailbox.id != 0) {
556 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(op.mailbox.id), 551 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(op.mailbox.id),
557 op.mailbox.data); 552 op.mailbox.data);
@@ -579,6 +574,22 @@ int gr_gk20a_submit_fecs_method_op(struct gk20a *g,
579 op.method.data, op.method.addr); 574 op.method.data, op.method.addr);
580 } 575 }
581 576
577 return ret;
578}
579
580/* The following is a less brittle way to call gr_gk20a_submit_fecs_method(...)
581 * We should replace most, if not all, fecs method calls to this instead. */
582int gr_gk20a_submit_fecs_method_op(struct gk20a *g,
583 struct fecs_method_op_gk20a op,
584 bool sleepduringwait)
585{
586 struct gr_gk20a *gr = &g->gr;
587 int ret;
588
589 nvgpu_mutex_acquire(&gr->fecs_mutex);
590
591 ret = gr_gk20a_submit_fecs_method_op_locked(g, op, sleepduringwait);
592
582 nvgpu_mutex_release(&gr->fecs_mutex); 593 nvgpu_mutex_release(&gr->fecs_mutex);
583 594
584 return ret; 595 return ret;
@@ -2486,6 +2497,16 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g)
2486 return 0; 2497 return 0;
2487} 2498}
2488 2499
2500int gr_gk20a_set_fecs_watchdog_timeout(struct gk20a *g)
2501{
2502 gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0xffffffff);
2503 gk20a_writel(g, gr_fecs_method_data_r(), 0x7fffffff);
2504 gk20a_writel(g, gr_fecs_method_push_r(),
2505 gr_fecs_method_push_adr_set_watchdog_timeout_f());
2506
2507 return 0;
2508}
2509
2489static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g) 2510static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g)
2490{ 2511{
2491 u32 ret; 2512 u32 ret;
@@ -2507,10 +2528,11 @@ static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g)
2507 gr_fecs_current_ctx_valid_false_f()); 2528 gr_fecs_current_ctx_valid_false_f());
2508 } 2529 }
2509 2530
2510 gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0xffffffff); 2531 ret = g->ops.gr.set_fecs_watchdog_timeout(g);
2511 gk20a_writel(g, gr_fecs_method_data_r(), 0x7fffffff); 2532 if (ret) {
2512 gk20a_writel(g, gr_fecs_method_push_r(), 2533 nvgpu_err(g, "fail to set watchdog timeout");
2513 gr_fecs_method_push_adr_set_watchdog_timeout_f()); 2534 return ret;
2535 }
2514 2536
2515 nvgpu_log_fn(g, "done"); 2537 nvgpu_log_fn(g, "done");
2516 return 0; 2538 return 0;