diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f3b580e4..2a871b5a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -60,7 +60,6 @@ | |||
60 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 60 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
61 | #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h> | 61 | #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h> |
62 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 62 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
63 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> | ||
64 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> | 63 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> |
65 | 64 | ||
66 | #define BLK_SIZE (256) | 65 | #define BLK_SIZE (256) |
@@ -3153,9 +3152,6 @@ static void gk20a_remove_gr_support(struct gr_gk20a *gr) | |||
3153 | 3152 | ||
3154 | gr_gk20a_free_global_ctx_buffers(g); | 3153 | gr_gk20a_free_global_ctx_buffers(g); |
3155 | 3154 | ||
3156 | nvgpu_dma_free(g, &gr->mmu_wr_mem); | ||
3157 | nvgpu_dma_free(g, &gr->mmu_rd_mem); | ||
3158 | |||
3159 | nvgpu_dma_free(g, &gr->compbit_store.mem); | 3155 | nvgpu_dma_free(g, &gr->compbit_store.mem); |
3160 | 3156 | ||
3161 | memset(&gr->compbit_store, 0, sizeof(struct compbit_store_desc)); | 3157 | memset(&gr->compbit_store, 0, sizeof(struct compbit_store_desc)); |
@@ -3495,31 +3491,6 @@ clean_up: | |||
3495 | return -ENOMEM; | 3491 | return -ENOMEM; |
3496 | } | 3492 | } |
3497 | 3493 | ||
3498 | static int gr_gk20a_init_mmu_sw(struct gk20a *g, struct gr_gk20a *gr) | ||
3499 | { | ||
3500 | int err; | ||
3501 | |||
3502 | if (!nvgpu_mem_is_valid(&gr->mmu_wr_mem)) { | ||
3503 | err = nvgpu_dma_alloc_sys(g, 0x1000, &gr->mmu_wr_mem); | ||
3504 | if (err) { | ||
3505 | goto err; | ||
3506 | } | ||
3507 | } | ||
3508 | |||
3509 | if (!nvgpu_mem_is_valid(&gr->mmu_rd_mem)) { | ||
3510 | err = nvgpu_dma_alloc_sys(g, 0x1000, &gr->mmu_rd_mem); | ||
3511 | if (err) { | ||
3512 | goto err_free_wr_mem; | ||
3513 | } | ||
3514 | } | ||
3515 | return 0; | ||
3516 | |||
3517 | err_free_wr_mem: | ||
3518 | nvgpu_dma_free(g, &gr->mmu_wr_mem); | ||
3519 | err: | ||
3520 | return -ENOMEM; | ||
3521 | } | ||
3522 | |||
3523 | static u32 prime_set[18] = { | 3494 | static u32 prime_set[18] = { |
3524 | 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61 }; | 3495 | 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61 }; |
3525 | 3496 | ||
@@ -4529,35 +4500,11 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4529 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; | 4500 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; |
4530 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; | 4501 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; |
4531 | u32 data; | 4502 | u32 data; |
4532 | u64 addr; | ||
4533 | u32 last_method_data = 0; | 4503 | u32 last_method_data = 0; |
4534 | u32 i, err; | 4504 | u32 i, err; |
4535 | 4505 | ||
4536 | nvgpu_log_fn(g, " "); | 4506 | nvgpu_log_fn(g, " "); |
4537 | 4507 | ||
4538 | /* init mmu debug buffer */ | ||
4539 | addr = nvgpu_mem_get_addr(g, &gr->mmu_wr_mem); | ||
4540 | addr >>= fb_mmu_debug_wr_addr_alignment_v(); | ||
4541 | |||
4542 | gk20a_writel(g, fb_mmu_debug_wr_r(), | ||
4543 | nvgpu_aperture_mask(g, &gr->mmu_wr_mem, | ||
4544 | fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), | ||
4545 | fb_mmu_debug_wr_aperture_sys_mem_coh_f(), | ||
4546 | fb_mmu_debug_wr_aperture_vid_mem_f()) | | ||
4547 | fb_mmu_debug_wr_vol_false_f() | | ||
4548 | fb_mmu_debug_wr_addr_f(addr)); | ||
4549 | |||
4550 | addr = nvgpu_mem_get_addr(g, &gr->mmu_rd_mem); | ||
4551 | addr >>= fb_mmu_debug_rd_addr_alignment_v(); | ||
4552 | |||
4553 | gk20a_writel(g, fb_mmu_debug_rd_r(), | ||
4554 | nvgpu_aperture_mask(g, &gr->mmu_rd_mem, | ||
4555 | fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), | ||
4556 | fb_mmu_debug_wr_aperture_sys_mem_coh_f(), | ||
4557 | fb_mmu_debug_rd_aperture_vid_mem_f()) | | ||
4558 | fb_mmu_debug_rd_vol_false_f() | | ||
4559 | fb_mmu_debug_rd_addr_f(addr)); | ||
4560 | |||
4561 | if (g->ops.gr.init_gpc_mmu) { | 4508 | if (g->ops.gr.init_gpc_mmu) { |
4562 | g->ops.gr.init_gpc_mmu(g); | 4509 | g->ops.gr.init_gpc_mmu(g); |
4563 | } | 4510 | } |
@@ -4940,11 +4887,6 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g) | |||
4940 | goto clean_up; | 4887 | goto clean_up; |
4941 | } | 4888 | } |
4942 | 4889 | ||
4943 | err = gr_gk20a_init_mmu_sw(g, gr); | ||
4944 | if (err) { | ||
4945 | goto clean_up; | ||
4946 | } | ||
4947 | |||
4948 | err = gr_gk20a_init_map_tiles(g, gr); | 4890 | err = gr_gk20a_init_map_tiles(g, gr); |
4949 | if (err) { | 4891 | if (err) { |
4950 | goto clean_up; | 4892 | goto clean_up; |