1 files changed, 7 insertions, 97 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 9e4d3c37..a4c1ce58 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -43,6 +43,8 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/unit.h>
+#include <nvgpu/power_features/pg.h>
+#include <nvgpu/power_features/cg.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -91,8 +93,6 @@ static void gr_gk20a_free_channel_patch_ctx(struct gk20a *g,
 /* golden ctx image */
 static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
                                           struct channel_gk20a *c);
-/*elcg init */
-static void gr_gk20a_enable_elcg(struct gk20a *g);
 
 int gr_gk20a_get_ctx_id(struct gk20a *g,
                 struct channel_gk20a *c,
@@ -4227,33 +4227,6 @@ int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
                 gr_gk20a_add_zbc(g, gr, zbc_val));
 }
 
-void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
-{
-        u32 engine_idx;
-        u32 active_engine_id = 0;
-        struct fifo_engine_info_gk20a *engine_info = NULL;
-        struct fifo_gk20a *f = &g->fifo;
-
-        for (engine_idx = 0; engine_idx < f->num_engines; ++engine_idx) {
-                active_engine_id = f->active_engines_list[engine_idx];
-                engine_info = &f->engine_info[active_engine_id];
-
-                /* gr_engine supports both BLCG and ELCG */
-                if ((cgmode == BLCG_MODE) &&
-                        (engine_info->engine_enum == ENGINE_GR_GK20A)) {
-                                g->ops.therm.init_blcg_mode(g, mode_config, active_engine_id);
-                                break;
-                } else if (cgmode == ELCG_MODE) {
-                        g->ops.therm.init_elcg_mode(g, mode_config,
-                                                active_engine_id);
-                } else {
-                        nvgpu_err(g, "invalid cg mode %d, config %d for "
-                                                        "act_eng_id %d",
-                                        cgmode, mode_config, active_engine_id);
-                }
-        }
-}
-
 void gr_gk20a_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
                                                 u32 *zcull_map_tiles)
 {
@@ -4655,60 +4628,6 @@ out:
         return err;
 }
 
-static void gr_gk20a_load_gating_prod(struct gk20a *g)
-{
-        nvgpu_log_fn(g, " ");
-
-        /* slcg prod values */
-        if (g->ops.clock_gating.slcg_bus_load_gating_prod) {
-                g->ops.clock_gating.slcg_bus_load_gating_prod(g,
-                                g->slcg_enabled);
-        }
-        if (g->ops.clock_gating.slcg_chiplet_load_gating_prod) {
-                g->ops.clock_gating.slcg_chiplet_load_gating_prod(g,
-                                g->slcg_enabled);
-        }
-        if (g->ops.clock_gating.slcg_gr_load_gating_prod) {
-                g->ops.clock_gating.slcg_gr_load_gating_prod(g,
-                                g->slcg_enabled);
-        }
-        if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod) {
-                g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
-                                g->slcg_enabled);
-        }
-        if (g->ops.clock_gating.slcg_perf_load_gating_prod) {
-                g->ops.clock_gating.slcg_perf_load_gating_prod(g,
-                                g->slcg_enabled);
-        }
-        if (g->ops.clock_gating.slcg_xbar_load_gating_prod) {
-                g->ops.clock_gating.slcg_xbar_load_gating_prod(g,
-                                g->slcg_enabled);
-        }
-
-        /* blcg prod values */
-        if (g->ops.clock_gating.blcg_bus_load_gating_prod) {
-                g->ops.clock_gating.blcg_bus_load_gating_prod(g,
-                                g->blcg_enabled);
-        }
-        if (g->ops.clock_gating.blcg_gr_load_gating_prod) {
-                g->ops.clock_gating.blcg_gr_load_gating_prod(g,
-                                g->blcg_enabled);
-        }
-        if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod) {
-                g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
-                                g->blcg_enabled);
-        }
-        if (g->ops.clock_gating.blcg_xbar_load_gating_prod) {
-                g->ops.clock_gating.blcg_xbar_load_gating_prod(g,
-                                g->blcg_enabled);
-        }
-        if (g->ops.clock_gating.pg_gr_load_gating_prod) {
-                g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
-        }
-
-        nvgpu_log_fn(g, "done");
-}
-
 static int gk20a_init_gr_prepare(struct gk20a *g)
 {
         u32 err = 0;
@@ -4718,10 +4637,10 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
                         g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) |
                         g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
-        gr_gk20a_load_gating_prod(g);
+        nvgpu_cg_init_gr_load_gating_prod(g);
 
         /* Disable elcg until it gets enabled later in the init*/
-        gr_gk20a_init_cg_mode(g, ELCG_MODE, ELCG_RUN);
+        nvgpu_cg_elcg_disable(g);
 
         /* enable fifo access */
         gk20a_writel(g, gr_gpfifo_ctl_r(),
@@ -5041,7 +4960,7 @@ int gk20a_init_gr_support(struct gk20a *g)
                 }
         }
 
-        gr_gk20a_enable_elcg(g);
+        nvgpu_cg_elcg_enable(g);
         /* GR is inialized, signal possible waiters */
         g->gr.initialized = true;
         nvgpu_cond_signal(&g->gr.init_wq);
@@ -5128,15 +5047,6 @@ int gk20a_enable_gr_hw(struct gk20a *g)
         return 0;
 }
 
-static void gr_gk20a_enable_elcg(struct gk20a *g)
-{
-        if (g->elcg_enabled) {
-                gr_gk20a_init_cg_mode(g, ELCG_MODE, ELCG_AUTO);
-        } else {
-                gr_gk20a_init_cg_mode(g, ELCG_MODE, ELCG_RUN);
-        }
-}
-
 int gk20a_gr_reset(struct gk20a *g)
 {
         int err;
@@ -5193,8 +5103,8 @@ int gk20a_gr_reset(struct gk20a *g)
                 return err;
         }
 
-        gr_gk20a_load_gating_prod(g);
-        gr_gk20a_enable_elcg(g);
+        nvgpu_cg_init_gr_load_gating_prod(g);
+        nvgpu_cg_elcg_enable(g);
 
         return err;
 }