1 files changed, 41 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index a4c1ce58..788ebf45 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -628,7 +628,14 @@ static int gr_gk20a_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, u32 *ret)
                       .cond.fail = GR_IS_UCODE_OP_EQUAL }, true);
 }
 
-/* Stop processing (stall) context switches at FECS. */
+/**
+ * Stop processing (stall) context switches at FECS:-
+ * If fecs is sent stop_ctxsw method, elpg entry/exit cannot happen
+ * and may timeout. It could manifest as different error signatures
+ * depending on when stop_ctxsw fecs method gets sent with respect
+ * to pmu elpg sequence. It could come as pmu halt or abort or
+ * maybe ext error too.
+*/
 int gr_gk20a_disable_ctxsw(struct gk20a *g)
 {
         int err = 0;
@@ -638,8 +645,24 @@ int gr_gk20a_disable_ctxsw(struct gk20a *g)
         nvgpu_mutex_acquire(&g->ctxsw_disable_lock);
         g->ctxsw_disable_count++;
         if (g->ctxsw_disable_count == 1) {
-                err = gr_gk20a_ctrl_ctxsw(g,
+                err = nvgpu_pg_elpg_disable(g);
+                if (err != 0) {
+                        nvgpu_err(g, "failed to disable elpg. not safe to "
+                                        "stop_ctxsw");
+                        /* stop ctxsw command is not sent */
+                        g->ctxsw_disable_count--;
+                } else {
+                        err = gr_gk20a_ctrl_ctxsw(g,
                                 gr_fecs_method_push_adr_stop_ctxsw_v(), NULL);
+                        if (err != 0) {
+                                nvgpu_err(g, "failed to stop fecs ctxsw");
+                                /* stop ctxsw failed */
+                                g->ctxsw_disable_count--;
+                        }
+                }
+        } else {
+                nvgpu_log_info(g, "ctxsw disabled, ctxsw_disable_count: %d",
+                        g->ctxsw_disable_count);
         }
         nvgpu_mutex_release(&g->ctxsw_disable_lock);
 
@@ -654,12 +677,28 @@ int gr_gk20a_enable_ctxsw(struct gk20a *g)
         nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, " ");
 
         nvgpu_mutex_acquire(&g->ctxsw_disable_lock);
+
+        if (g->ctxsw_disable_count == 0) {
+                goto ctxsw_already_enabled;
+        }
         g->ctxsw_disable_count--;
         WARN_ON(g->ctxsw_disable_count < 0);
         if (g->ctxsw_disable_count == 0) {
                 err = gr_gk20a_ctrl_ctxsw(g,
                                 gr_fecs_method_push_adr_start_ctxsw_v(), NULL);
+                if (err != 0) {
+                        nvgpu_err(g, "failed to start fecs ctxsw");
+                } else {
+                        if (nvgpu_pg_elpg_enable(g) != 0) {
+                                nvgpu_err(g, "failed to enable elpg "
+                                        "after start_ctxsw");
+                        }
+                }
+        } else {
+                nvgpu_log_info(g, "ctxsw_disable_count: %d is not 0 yet",
+                        g->ctxsw_disable_count);
         }
+ctxsw_already_enabled:
         nvgpu_mutex_release(&g->ctxsw_disable_lock);
 
         return err;