diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6a41509b..df85d852 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -655,8 +655,6 @@ static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
655 | 655 | ||
656 | gk20a_dbg_fn(""); | 656 | gk20a_dbg_fn(""); |
657 | 657 | ||
658 | gk20a_mm_fb_flush(c->g); | ||
659 | |||
660 | inst_ptr = c->inst_block.cpuva; | 658 | inst_ptr = c->inst_block.cpuva; |
661 | if (!inst_ptr) | 659 | if (!inst_ptr) |
662 | return -ENOMEM; | 660 | return -ENOMEM; |
@@ -1573,7 +1571,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1573 | ctx_header_words = roundup(ctx_header_bytes, sizeof(u32)); | 1571 | ctx_header_words = roundup(ctx_header_bytes, sizeof(u32)); |
1574 | ctx_header_words >>= 2; | 1572 | ctx_header_words >>= 2; |
1575 | 1573 | ||
1576 | gk20a_mm_fb_flush(g); | 1574 | gk20a_mm_l2_flush(g, true); |
1577 | 1575 | ||
1578 | for (i = 0; i < ctx_header_words; i++) { | 1576 | for (i = 0; i < ctx_header_words; i++) { |
1579 | data = gk20a_mem_rd32(ctx_ptr, i); | 1577 | data = gk20a_mem_rd32(ctx_ptr, i); |
@@ -1634,11 +1632,9 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, | |||
1634 | void *ctx_ptr = NULL; | 1632 | void *ctx_ptr = NULL; |
1635 | u32 data; | 1633 | u32 data; |
1636 | 1634 | ||
1637 | /*XXX caller responsible for making sure the channel is quiesced? */ | ||
1638 | |||
1639 | /* Channel gr_ctx buffer is gpu cacheable. | 1635 | /* Channel gr_ctx buffer is gpu cacheable. |
1640 | Flush and invalidate before cpu update. */ | 1636 | Flush and invalidate before cpu update. */ |
1641 | gk20a_mm_fb_flush(g); | 1637 | gk20a_mm_l2_flush(g, true); |
1642 | 1638 | ||
1643 | ctx_ptr = vmap(ch_ctx->gr_ctx.pages, | 1639 | ctx_ptr = vmap(ch_ctx->gr_ctx.pages, |
1644 | PAGE_ALIGN(ch_ctx->gr_ctx.size) >> PAGE_SHIFT, | 1640 | PAGE_ALIGN(ch_ctx->gr_ctx.size) >> PAGE_SHIFT, |
@@ -1678,7 +1674,7 @@ static int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1678 | 1674 | ||
1679 | /* Channel gr_ctx buffer is gpu cacheable. | 1675 | /* Channel gr_ctx buffer is gpu cacheable. |
1680 | Flush and invalidate before cpu update. */ | 1676 | Flush and invalidate before cpu update. */ |
1681 | gk20a_mm_fb_flush(g); | 1677 | gk20a_mm_l2_flush(g, true); |
1682 | 1678 | ||
1683 | ctx_ptr = vmap(ch_ctx->gr_ctx.pages, | 1679 | ctx_ptr = vmap(ch_ctx->gr_ctx.pages, |
1684 | PAGE_ALIGN(ch_ctx->gr_ctx.size) >> PAGE_SHIFT, | 1680 | PAGE_ALIGN(ch_ctx->gr_ctx.size) >> PAGE_SHIFT, |
@@ -6686,7 +6682,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
6686 | goto cleanup; | 6682 | goto cleanup; |
6687 | } | 6683 | } |
6688 | 6684 | ||
6689 | gk20a_mm_fb_flush(g); | 6685 | gk20a_mm_l2_flush(g, true); |
6690 | 6686 | ||
6691 | /* write to appropriate place in context image, | 6687 | /* write to appropriate place in context image, |
6692 | * first have to figure out where that really is */ | 6688 | * first have to figure out where that really is */ |