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path: root/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c39
1 files changed, 0 insertions, 39 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 6a9e1753..4217658c 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4176,45 +4176,6 @@ void gr_gk20a_enable_hww_exceptions(struct gk20a *g)
4176 gk20a_writel(g, gr_memfmt_hww_esr_r(), 4176 gk20a_writel(g, gr_memfmt_hww_esr_r(),
4177 gr_memfmt_hww_esr_en_enable_f() | 4177 gr_memfmt_hww_esr_en_enable_f() |
4178 gr_memfmt_hww_esr_reset_active_f()); 4178 gr_memfmt_hww_esr_reset_active_f());
4179 gk20a_writel(g, gr_scc_hww_esr_r(),
4180 gr_scc_hww_esr_en_enable_f() |
4181 gr_scc_hww_esr_reset_active_f());
4182 gk20a_writel(g, gr_mme_hww_esr_r(),
4183 gr_mme_hww_esr_en_enable_f() |
4184 gr_mme_hww_esr_reset_active_f());
4185 gk20a_writel(g, gr_pd_hww_esr_r(),
4186 gr_pd_hww_esr_en_enable_f() |
4187 gr_pd_hww_esr_reset_active_f());
4188 gk20a_writel(g, gr_sked_hww_esr_r(), /* enabled by default */
4189 gr_sked_hww_esr_reset_active_f());
4190 gk20a_writel(g, gr_ds_hww_esr_r(),
4191 gr_ds_hww_esr_en_enabled_f() |
4192 gr_ds_hww_esr_reset_task_f());
4193 gk20a_writel(g, gr_ds_hww_report_mask_r(),
4194 gr_ds_hww_report_mask_sph0_err_report_f() |
4195 gr_ds_hww_report_mask_sph1_err_report_f() |
4196 gr_ds_hww_report_mask_sph2_err_report_f() |
4197 gr_ds_hww_report_mask_sph3_err_report_f() |
4198 gr_ds_hww_report_mask_sph4_err_report_f() |
4199 gr_ds_hww_report_mask_sph5_err_report_f() |
4200 gr_ds_hww_report_mask_sph6_err_report_f() |
4201 gr_ds_hww_report_mask_sph7_err_report_f() |
4202 gr_ds_hww_report_mask_sph8_err_report_f() |
4203 gr_ds_hww_report_mask_sph9_err_report_f() |
4204 gr_ds_hww_report_mask_sph10_err_report_f() |
4205 gr_ds_hww_report_mask_sph11_err_report_f() |
4206 gr_ds_hww_report_mask_sph12_err_report_f() |
4207 gr_ds_hww_report_mask_sph13_err_report_f() |
4208 gr_ds_hww_report_mask_sph14_err_report_f() |
4209 gr_ds_hww_report_mask_sph15_err_report_f() |
4210 gr_ds_hww_report_mask_sph16_err_report_f() |
4211 gr_ds_hww_report_mask_sph17_err_report_f() |
4212 gr_ds_hww_report_mask_sph18_err_report_f() |
4213 gr_ds_hww_report_mask_sph19_err_report_f() |
4214 gr_ds_hww_report_mask_sph20_err_report_f() |
4215 gr_ds_hww_report_mask_sph21_err_report_f() |
4216 gr_ds_hww_report_mask_sph22_err_report_f() |
4217 gr_ds_hww_report_mask_sph23_err_report_f());
4218} 4179}
4219 4180
4220static void gr_gk20a_set_hww_esr_report_mask(struct gk20a *g) 4181static void gr_gk20a_set_hww_esr_report_mask(struct gk20a *g)