diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 68ad7bcd..c7b00500 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4344,6 +4344,16 @@ void gr_gk20a_enable_hww_exceptions(struct gk20a *g) | |||
4344 | gr_memfmt_hww_esr_reset_active_f()); | 4344 | gr_memfmt_hww_esr_reset_active_f()); |
4345 | } | 4345 | } |
4346 | 4346 | ||
4347 | void gr_gk20a_fecs_host_int_enable(struct gk20a *g) | ||
4348 | { | ||
4349 | gk20a_writel(g, gr_fecs_host_int_enable_r(), | ||
4350 | gr_fecs_host_int_enable_ctxsw_intr1_enable_f() | | ||
4351 | gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() | | ||
4352 | gr_fecs_host_int_enable_umimp_firmware_method_enable_f() | | ||
4353 | gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | | ||
4354 | gr_fecs_host_int_enable_watchdog_enable_f()); | ||
4355 | } | ||
4356 | |||
4347 | static int gk20a_init_gr_setup_hw(struct gk20a *g) | 4357 | static int gk20a_init_gr_setup_hw(struct gk20a *g) |
4348 | { | 4358 | { |
4349 | struct gr_gk20a *gr = &g->gr; | 4359 | struct gr_gk20a *gr = &g->gr; |
@@ -4407,12 +4417,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4407 | gk20a_writel(g, gr_intr_en_r(), 0xFFFFFFFF); | 4417 | gk20a_writel(g, gr_intr_en_r(), 0xFFFFFFFF); |
4408 | 4418 | ||
4409 | /* enable fecs error interrupts */ | 4419 | /* enable fecs error interrupts */ |
4410 | gk20a_writel(g, gr_fecs_host_int_enable_r(), | 4420 | g->ops.gr.fecs_host_int_enable(g); |
4411 | gr_fecs_host_int_enable_ctxsw_intr1_enable_f() | | ||
4412 | gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() | | ||
4413 | gr_fecs_host_int_enable_umimp_firmware_method_enable_f() | | ||
4414 | gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | | ||
4415 | gr_fecs_host_int_enable_watchdog_enable_f()); | ||
4416 | 4421 | ||
4417 | g->ops.gr.enable_hww_exceptions(g); | 4422 | g->ops.gr.enable_hww_exceptions(g); |
4418 | g->ops.gr.set_hww_esr_report_mask(g); | 4423 | g->ops.gr.set_hww_esr_report_mask(g); |
@@ -5124,15 +5129,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | |||
5124 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); | 5129 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); |
5125 | int ret = 0; | 5130 | int ret = 0; |
5126 | 5131 | ||
5127 | gk20a_dbg_fn(""); | ||
5128 | |||
5129 | if (!gr_fecs_intr) | 5132 | if (!gr_fecs_intr) |
5130 | return 0; | 5133 | return 0; |
5131 | 5134 | ||
5132 | nvgpu_err(g, | ||
5133 | "unhandled fecs error interrupt 0x%08x for channel %u", | ||
5134 | gr_fecs_intr, isr_data->chid); | ||
5135 | |||
5136 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { | 5135 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { |
5137 | gk20a_gr_set_error_notifier(g, isr_data, | 5136 | gk20a_gr_set_error_notifier(g, isr_data, |
5138 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); | 5137 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); |
@@ -5141,6 +5140,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | |||
5141 | gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)), | 5140 | gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)), |
5142 | isr_data->data_lo); | 5141 | isr_data->data_lo); |
5143 | ret = -1; | 5142 | ret = -1; |
5143 | } else { | ||
5144 | nvgpu_err(g, | ||
5145 | "fecs error interrupt 0x%08x for channel %u", | ||
5146 | gr_fecs_intr, isr_data->chid); | ||
5144 | } | 5147 | } |
5145 | 5148 | ||
5146 | gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); | 5149 | gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); |