diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 71 |
1 files changed, 2 insertions, 69 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 5539b801..bb54e00e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -61,7 +61,6 @@ | |||
61 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 61 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
62 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | 62 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> |
63 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> | 63 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> |
64 | #include <nvgpu/hw/gk20a/hw_therm_gk20a.h> | ||
65 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> | 64 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> |
66 | 65 | ||
67 | #define BLK_SIZE (256) | 66 | #define BLK_SIZE (256) |
@@ -4116,72 +4115,6 @@ int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | |||
4116 | gr_gk20a_add_zbc(g, gr, zbc_val)); | 4115 | gr_gk20a_add_zbc(g, gr, zbc_val)); |
4117 | } | 4116 | } |
4118 | 4117 | ||
4119 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) | ||
4120 | { | ||
4121 | u32 gate_ctrl; | ||
4122 | |||
4123 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
4124 | return; | ||
4125 | |||
4126 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | ||
4127 | |||
4128 | switch (mode) { | ||
4129 | case BLCG_RUN: | ||
4130 | gate_ctrl = set_field(gate_ctrl, | ||
4131 | therm_gate_ctrl_blk_clk_m(), | ||
4132 | therm_gate_ctrl_blk_clk_run_f()); | ||
4133 | break; | ||
4134 | case BLCG_AUTO: | ||
4135 | gate_ctrl = set_field(gate_ctrl, | ||
4136 | therm_gate_ctrl_blk_clk_m(), | ||
4137 | therm_gate_ctrl_blk_clk_auto_f()); | ||
4138 | break; | ||
4139 | default: | ||
4140 | nvgpu_err(g, | ||
4141 | "invalid blcg mode %d", mode); | ||
4142 | return; | ||
4143 | } | ||
4144 | |||
4145 | gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); | ||
4146 | } | ||
4147 | |||
4148 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | ||
4149 | { | ||
4150 | u32 gate_ctrl; | ||
4151 | |||
4152 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | ||
4153 | |||
4154 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) | ||
4155 | return; | ||
4156 | |||
4157 | switch (mode) { | ||
4158 | case ELCG_RUN: | ||
4159 | gate_ctrl = set_field(gate_ctrl, | ||
4160 | therm_gate_ctrl_eng_clk_m(), | ||
4161 | therm_gate_ctrl_eng_clk_run_f()); | ||
4162 | gate_ctrl = set_field(gate_ctrl, | ||
4163 | therm_gate_ctrl_eng_pwr_m(), | ||
4164 | /* set elpg to auto to meet hw expectation */ | ||
4165 | therm_gate_ctrl_eng_pwr_auto_f()); | ||
4166 | break; | ||
4167 | case ELCG_STOP: | ||
4168 | gate_ctrl = set_field(gate_ctrl, | ||
4169 | therm_gate_ctrl_eng_clk_m(), | ||
4170 | therm_gate_ctrl_eng_clk_stop_f()); | ||
4171 | break; | ||
4172 | case ELCG_AUTO: | ||
4173 | gate_ctrl = set_field(gate_ctrl, | ||
4174 | therm_gate_ctrl_eng_clk_m(), | ||
4175 | therm_gate_ctrl_eng_clk_auto_f()); | ||
4176 | break; | ||
4177 | default: | ||
4178 | nvgpu_err(g, | ||
4179 | "invalid elcg mode %d", mode); | ||
4180 | } | ||
4181 | |||
4182 | gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); | ||
4183 | } | ||
4184 | |||
4185 | void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config) | 4118 | void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config) |
4186 | { | 4119 | { |
4187 | u32 engine_idx; | 4120 | u32 engine_idx; |
@@ -4196,10 +4129,10 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config) | |||
4196 | /* gr_engine supports both BLCG and ELCG */ | 4129 | /* gr_engine supports both BLCG and ELCG */ |
4197 | if ((cgmode == BLCG_MODE) && | 4130 | if ((cgmode == BLCG_MODE) && |
4198 | (engine_info->engine_enum == ENGINE_GR_GK20A)) { | 4131 | (engine_info->engine_enum == ENGINE_GR_GK20A)) { |
4199 | gr_gk20a_init_blcg_mode(g, mode_config, active_engine_id); | 4132 | g->ops.therm.init_blcg_mode(g, mode_config, active_engine_id); |
4200 | break; | 4133 | break; |
4201 | } else if (cgmode == ELCG_MODE) | 4134 | } else if (cgmode == ELCG_MODE) |
4202 | g->ops.gr.init_elcg_mode(g, mode_config, | 4135 | g->ops.therm.init_elcg_mode(g, mode_config, |
4203 | active_engine_id); | 4136 | active_engine_id); |
4204 | else | 4137 | else |
4205 | nvgpu_err(g, "invalid cg mode %d, config %d for " | 4138 | nvgpu_err(g, "invalid cg mode %d, config %d for " |