diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index cbad1292..661a2ca3 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4246,10 +4246,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4246 | if (g->ops.gr.init_gpc_mmu) | 4246 | if (g->ops.gr.init_gpc_mmu) |
4247 | g->ops.gr.init_gpc_mmu(g); | 4247 | g->ops.gr.init_gpc_mmu(g); |
4248 | 4248 | ||
4249 | /* slcg prod values */ | ||
4250 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled); | ||
4251 | g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled); | ||
4252 | |||
4253 | /* init mmu debug buffer */ | 4249 | /* init mmu debug buffer */ |
4254 | addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova); | 4250 | addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova); |
4255 | addr_lo = u64_lo32(addr); | 4251 | addr_lo = u64_lo32(addr); |
@@ -4281,9 +4277,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4281 | 4277 | ||
4282 | gr_gk20a_zcull_init_hw(g, gr); | 4278 | gr_gk20a_zcull_init_hw(g, gr); |
4283 | 4279 | ||
4284 | g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled); | ||
4285 | g->ops.clock_gating.pg_gr_load_gating_prod(g, true); | ||
4286 | |||
4287 | if (g->elcg_enabled) { | 4280 | if (g->elcg_enabled) { |
4288 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A); | 4281 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A); |
4289 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A); | 4282 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A); |
@@ -4426,6 +4419,19 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4426 | | mc_enable_blg_enabled_f() | 4419 | | mc_enable_blg_enabled_f() |
4427 | | mc_enable_perfmon_enabled_f()); | 4420 | | mc_enable_perfmon_enabled_f()); |
4428 | 4421 | ||
4422 | /* slcg prod values */ | ||
4423 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled); | ||
4424 | if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod) | ||
4425 | g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g, | ||
4426 | g->slcg_enabled); | ||
4427 | g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled); | ||
4428 | |||
4429 | g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled); | ||
4430 | if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod) | ||
4431 | g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g, | ||
4432 | g->blcg_enabled); | ||
4433 | g->ops.clock_gating.pg_gr_load_gating_prod(g, true); | ||
4434 | |||
4429 | /* enable fifo access */ | 4435 | /* enable fifo access */ |
4430 | gk20a_writel(g, gr_gpfifo_ctl_r(), | 4436 | gk20a_writel(g, gr_gpfifo_ctl_r(), |
4431 | gr_gpfifo_ctl_access_enabled_f() | | 4437 | gr_gpfifo_ctl_access_enabled_f() | |