diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 2ee2048c..a9632eaa 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -725,7 +725,7 @@ static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, | |||
725 | u32 ret; | 725 | u32 ret; |
726 | 726 | ||
727 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", | 727 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", |
728 | c->hw_chid, inst_base_ptr); | 728 | c->chid, inst_base_ptr); |
729 | 729 | ||
730 | ret = gr_gk20a_submit_fecs_method_op(g, | 730 | ret = gr_gk20a_submit_fecs_method_op(g, |
731 | (struct fecs_method_op_gk20a) { | 731 | (struct fecs_method_op_gk20a) { |
@@ -5933,7 +5933,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx( | |||
5933 | /* check cache first */ | 5933 | /* check cache first */ |
5934 | for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) { | 5934 | for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) { |
5935 | if (gr->chid_tlb[i].curr_ctx == curr_ctx) { | 5935 | if (gr->chid_tlb[i].curr_ctx == curr_ctx) { |
5936 | chid = gr->chid_tlb[i].hw_chid; | 5936 | chid = gr->chid_tlb[i].chid; |
5937 | tsgid = gr->chid_tlb[i].tsgid; | 5937 | tsgid = gr->chid_tlb[i].tsgid; |
5938 | ret = gk20a_channel_get(&f->channel[chid]); | 5938 | ret = gk20a_channel_get(&f->channel[chid]); |
5939 | goto unlock; | 5939 | goto unlock; |
@@ -5964,7 +5964,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx( | |||
5964 | for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) { | 5964 | for (i = 0; i < GR_CHANNEL_MAP_TLB_SIZE; i++) { |
5965 | if (gr->chid_tlb[i].curr_ctx == 0) { | 5965 | if (gr->chid_tlb[i].curr_ctx == 0) { |
5966 | gr->chid_tlb[i].curr_ctx = curr_ctx; | 5966 | gr->chid_tlb[i].curr_ctx = curr_ctx; |
5967 | gr->chid_tlb[i].hw_chid = chid; | 5967 | gr->chid_tlb[i].chid = chid; |
5968 | gr->chid_tlb[i].tsgid = tsgid; | 5968 | gr->chid_tlb[i].tsgid = tsgid; |
5969 | goto unlock; | 5969 | goto unlock; |
5970 | } | 5970 | } |
@@ -5972,7 +5972,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx( | |||
5972 | 5972 | ||
5973 | /* no free entry, flush one */ | 5973 | /* no free entry, flush one */ |
5974 | gr->chid_tlb[gr->channel_tlb_flush_index].curr_ctx = curr_ctx; | 5974 | gr->chid_tlb[gr->channel_tlb_flush_index].curr_ctx = curr_ctx; |
5975 | gr->chid_tlb[gr->channel_tlb_flush_index].hw_chid = chid; | 5975 | gr->chid_tlb[gr->channel_tlb_flush_index].chid = chid; |
5976 | gr->chid_tlb[gr->channel_tlb_flush_index].tsgid = tsgid; | 5976 | gr->chid_tlb[gr->channel_tlb_flush_index].tsgid = tsgid; |
5977 | 5977 | ||
5978 | gr->channel_tlb_flush_index = | 5978 | gr->channel_tlb_flush_index = |
@@ -6514,7 +6514,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6514 | 6514 | ||
6515 | ch = gk20a_gr_get_channel_from_ctx(g, isr_data.curr_ctx, &tsgid); | 6515 | ch = gk20a_gr_get_channel_from_ctx(g, isr_data.curr_ctx, &tsgid); |
6516 | if (ch) { | 6516 | if (ch) { |
6517 | isr_data.chid = ch->hw_chid; | 6517 | isr_data.chid = ch->chid; |
6518 | } else { | 6518 | } else { |
6519 | isr_data.chid = FIFO_INVAL_CHANNEL_ID; | 6519 | isr_data.chid = FIFO_INVAL_CHANNEL_ID; |
6520 | nvgpu_err(g, "ch id is INVALID 0xffffffff"); | 6520 | nvgpu_err(g, "ch id is INVALID 0xffffffff"); |
@@ -6626,7 +6626,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6626 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | 6626 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, |
6627 | "GPC exception pending"); | 6627 | "GPC exception pending"); |
6628 | 6628 | ||
6629 | fault_ch = gk20a_fifo_channel_from_hw_chid(g, | 6629 | fault_ch = gk20a_fifo_channel_from_chid(g, |
6630 | isr_data.chid); | 6630 | isr_data.chid); |
6631 | 6631 | ||
6632 | /*isr_data.chid can be ~0 and fault_ch can be NULL */ | 6632 | /*isr_data.chid can be ~0 and fault_ch can be NULL */ |
@@ -6673,7 +6673,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6673 | tsgid, true, true, true); | 6673 | tsgid, true, true, true); |
6674 | else if (ch) | 6674 | else if (ch) |
6675 | gk20a_fifo_recover(g, gr_engine_id, | 6675 | gk20a_fifo_recover(g, gr_engine_id, |
6676 | ch->hw_chid, false, true, true); | 6676 | ch->chid, false, true, true); |
6677 | else | 6677 | else |
6678 | gk20a_fifo_recover(g, gr_engine_id, | 6678 | gk20a_fifo_recover(g, gr_engine_id, |
6679 | 0, false, false, true); | 6679 | 0, false, false, true); |
@@ -8337,16 +8337,16 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) | |||
8337 | 8337 | ||
8338 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 8338 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
8339 | "curr_gr_chid=%d curr_tsgid=%d, ch->tsgid=%d" | 8339 | "curr_gr_chid=%d curr_tsgid=%d, ch->tsgid=%d" |
8340 | " ch->hw_chid=%d", | 8340 | " ch->chid=%d", |
8341 | curr_ch ? curr_ch->hw_chid : -1, | 8341 | curr_ch ? curr_ch->chid : -1, |
8342 | curr_gr_tsgid, | 8342 | curr_gr_tsgid, |
8343 | ch->tsgid, | 8343 | ch->tsgid, |
8344 | ch->hw_chid); | 8344 | ch->chid); |
8345 | 8345 | ||
8346 | if (!curr_ch) | 8346 | if (!curr_ch) |
8347 | return false; | 8347 | return false; |
8348 | 8348 | ||
8349 | if (ch->hw_chid == curr_ch->hw_chid) | 8349 | if (ch->chid == curr_ch->chid) |
8350 | ret = true; | 8350 | ret = true; |
8351 | 8351 | ||
8352 | if (gk20a_is_channel_marked_as_tsg(ch) && (ch->tsgid == curr_gr_tsgid)) | 8352 | if (gk20a_is_channel_marked_as_tsg(ch) && (ch->tsgid == curr_gr_tsgid)) |