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path: root/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 2b5d809f..c12f49ac 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -29,6 +29,7 @@
29#include <nvgpu/sort.h> 29#include <nvgpu/sort.h>
30#include <nvgpu/bug.h> 30#include <nvgpu/bug.h>
31#include <nvgpu/firmware.h> 31#include <nvgpu/firmware.h>
32#include <nvgpu/enabled.h>
32 33
33#include "gk20a.h" 34#include "gk20a.h"
34#include "kind_gk20a.h" 35#include "kind_gk20a.h"
@@ -386,7 +387,7 @@ int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms,
386 u32 delay = expect_delay; 387 u32 delay = expect_delay;
387 struct nvgpu_timeout timeout; 388 struct nvgpu_timeout timeout;
388 389
389 if (g->is_fmodel) 390 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
390 return 0; 391 return 0;
391 392
392 gk20a_dbg_fn(""); 393 gk20a_dbg_fn("");
@@ -1597,7 +1598,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
1597 if (gr->ctx_vars.golden_image_initialized) { 1598 if (gr->ctx_vars.golden_image_initialized) {
1598 goto clean_up; 1599 goto clean_up;
1599 } 1600 }
1600 if (!g->is_fmodel) { 1601 if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
1601 struct nvgpu_timeout timeout; 1602 struct nvgpu_timeout timeout;
1602 1603
1603 nvgpu_timeout_init(g, &timeout, 1604 nvgpu_timeout_init(g, &timeout,
@@ -1642,7 +1643,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
1642 gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); 1643 gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
1643 nvgpu_udelay(10); 1644 nvgpu_udelay(10);
1644 1645
1645 if (!g->is_fmodel) { 1646 if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
1646 struct nvgpu_timeout timeout; 1647 struct nvgpu_timeout timeout;
1647 1648
1648 nvgpu_timeout_init(g, &timeout, 1649 nvgpu_timeout_init(g, &timeout,
@@ -2582,7 +2583,7 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g)
2582 2583
2583 gk20a_dbg_fn(""); 2584 gk20a_dbg_fn("");
2584 2585
2585 if (g->is_fmodel) { 2586 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
2586 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), 2587 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7),
2587 gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); 2588 gr_fecs_ctxsw_mailbox_value_f(0xc0de7777));
2588 gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), 2589 gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7),