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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 70abef78..42a807f6 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8123,7 +8123,7 @@ void gk20a_gr_resume_single_sm(struct gk20a *g,
8123 gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); 8123 gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
8124} 8124}
8125 8125
8126void gk20a_resume_all_sms(struct gk20a *g) 8126void gk20a_gr_resume_all_sms(struct gk20a *g)
8127{ 8127{
8128 u32 dbgr_control0; 8128 u32 dbgr_control0;
8129 /* 8129 /*
@@ -8236,7 +8236,7 @@ bool gr_gk20a_resume_context(struct channel_gk20a *ch)
8236 bool ctx_resident = false; 8236 bool ctx_resident = false;
8237 8237
8238 if (gk20a_is_channel_ctx_resident(ch)) { 8238 if (gk20a_is_channel_ctx_resident(ch)) {
8239 gk20a_resume_all_sms(g); 8239 g->ops.gr.resume_all_sms(g);
8240 ctx_resident = true; 8240 ctx_resident = true;
8241 } else { 8241 } else {
8242 gk20a_enable_channel_tsg(g, ch); 8242 gk20a_enable_channel_tsg(g, ch);
@@ -8438,7 +8438,7 @@ int gr_gk20a_resume_from_pause(struct gk20a *g)
8438 8438
8439 /* Now resume all sms, write a 0 to the stop trigger 8439 /* Now resume all sms, write a 0 to the stop trigger
8440 * then a 1 to the run trigger */ 8440 * then a 1 to the run trigger */
8441 gk20a_resume_all_sms(g); 8441 g->ops.gr.resume_all_sms(g);
8442 8442
8443 return err; 8443 return err;
8444} 8444}