diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 121f264a..ed1f9af9 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5136,7 +5136,7 @@ int gk20a_gr_reset(struct gk20a *g) | |||
5136 | return err; | 5136 | return err; |
5137 | } | 5137 | } |
5138 | 5138 | ||
5139 | void gk20a_gr_set_error_notifier(struct gk20a *g, | 5139 | static void gk20a_gr_set_error_notifier(struct gk20a *g, |
5140 | struct gr_gk20a_isr_data *isr_data, u32 error_notifier) | 5140 | struct gr_gk20a_isr_data *isr_data, u32 error_notifier) |
5141 | { | 5141 | { |
5142 | struct fifo_gk20a *f = &g->fifo; | 5142 | struct fifo_gk20a *f = &g->fifo; |
@@ -5169,7 +5169,7 @@ static int gk20a_gr_handle_semaphore_timeout_pending(struct gk20a *g, | |||
5169 | struct gr_gk20a_isr_data *isr_data) | 5169 | struct gr_gk20a_isr_data *isr_data) |
5170 | { | 5170 | { |
5171 | gk20a_dbg_fn(""); | 5171 | gk20a_dbg_fn(""); |
5172 | g->ops.gr.set_error_notifier(g, isr_data, | 5172 | gk20a_gr_set_error_notifier(g, isr_data, |
5173 | NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); | 5173 | NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); |
5174 | nvgpu_err(g, | 5174 | nvgpu_err(g, |
5175 | "gr semaphore timeout"); | 5175 | "gr semaphore timeout"); |
@@ -5180,7 +5180,7 @@ static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g, | |||
5180 | struct gr_gk20a_isr_data *isr_data) | 5180 | struct gr_gk20a_isr_data *isr_data) |
5181 | { | 5181 | { |
5182 | gk20a_dbg_fn(""); | 5182 | gk20a_dbg_fn(""); |
5183 | g->ops.gr.set_error_notifier(g, isr_data, | 5183 | gk20a_gr_set_error_notifier(g, isr_data, |
5184 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); | 5184 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); |
5185 | /* This is an unrecoverable error, reset is needed */ | 5185 | /* This is an unrecoverable error, reset is needed */ |
5186 | nvgpu_err(g, | 5186 | nvgpu_err(g, |
@@ -5195,7 +5195,7 @@ static int gk20a_gr_handle_illegal_method(struct gk20a *g, | |||
5195 | isr_data->class_num, isr_data->offset, | 5195 | isr_data->class_num, isr_data->offset, |
5196 | isr_data->data_lo); | 5196 | isr_data->data_lo); |
5197 | if (ret) { | 5197 | if (ret) { |
5198 | g->ops.gr.set_error_notifier(g, isr_data, | 5198 | gk20a_gr_set_error_notifier(g, isr_data, |
5199 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); | 5199 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); |
5200 | nvgpu_err(g, "invalid method class 0x%08x" | 5200 | nvgpu_err(g, "invalid method class 0x%08x" |
5201 | ", offset 0x%08x address 0x%08x", | 5201 | ", offset 0x%08x address 0x%08x", |
@@ -5208,7 +5208,7 @@ static int gk20a_gr_handle_illegal_class(struct gk20a *g, | |||
5208 | struct gr_gk20a_isr_data *isr_data) | 5208 | struct gr_gk20a_isr_data *isr_data) |
5209 | { | 5209 | { |
5210 | gk20a_dbg_fn(""); | 5210 | gk20a_dbg_fn(""); |
5211 | g->ops.gr.set_error_notifier(g, isr_data, | 5211 | gk20a_gr_set_error_notifier(g, isr_data, |
5212 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 5212 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
5213 | nvgpu_err(g, | 5213 | nvgpu_err(g, |
5214 | "invalid class 0x%08x, offset 0x%08x", | 5214 | "invalid class 0x%08x, offset 0x%08x", |
@@ -5226,7 +5226,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | |||
5226 | return 0; | 5226 | return 0; |
5227 | 5227 | ||
5228 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { | 5228 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { |
5229 | g->ops.gr.set_error_notifier(g, isr_data, | 5229 | gk20a_gr_set_error_notifier(g, isr_data, |
5230 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); | 5230 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); |
5231 | nvgpu_err(g, | 5231 | nvgpu_err(g, |
5232 | "firmware method error 0x%08x for offset 0x%04x", | 5232 | "firmware method error 0x%08x for offset 0x%04x", |
@@ -5252,7 +5252,7 @@ static int gk20a_gr_handle_class_error(struct gk20a *g, | |||
5252 | 5252 | ||
5253 | gr_class_error = | 5253 | gr_class_error = |
5254 | gr_class_error_code_v(gk20a_readl(g, gr_class_error_r())); | 5254 | gr_class_error_code_v(gk20a_readl(g, gr_class_error_r())); |
5255 | g->ops.gr.set_error_notifier(g, isr_data, | 5255 | gk20a_gr_set_error_notifier(g, isr_data, |
5256 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 5256 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
5257 | nvgpu_err(g, "class error 0x%08x, offset 0x%08x," | 5257 | nvgpu_err(g, "class error 0x%08x, offset 0x%08x," |
5258 | "sub channel 0x%08x mme generated %d," | 5258 | "sub channel 0x%08x mme generated %d," |
@@ -5281,7 +5281,7 @@ static int gk20a_gr_handle_firmware_method(struct gk20a *g, | |||
5281 | { | 5281 | { |
5282 | gk20a_dbg_fn(""); | 5282 | gk20a_dbg_fn(""); |
5283 | 5283 | ||
5284 | g->ops.gr.set_error_notifier(g, isr_data, | 5284 | gk20a_gr_set_error_notifier(g, isr_data, |
5285 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 5285 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
5286 | nvgpu_err(g, | 5286 | nvgpu_err(g, |
5287 | "firmware method 0x%08x, offset 0x%08x for channel %u", | 5287 | "firmware method 0x%08x, offset 0x%08x for channel %u", |
@@ -6085,7 +6085,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6085 | 6085 | ||
6086 | if (need_reset) { | 6086 | if (need_reset) { |
6087 | nvgpu_err(g, "set gr exception notifier"); | 6087 | nvgpu_err(g, "set gr exception notifier"); |
6088 | g->ops.gr.set_error_notifier(g, &isr_data, | 6088 | gk20a_gr_set_error_notifier(g, &isr_data, |
6089 | NVGPU_ERR_NOTIFIER_GR_EXCEPTION); | 6089 | NVGPU_ERR_NOTIFIER_GR_EXCEPTION); |
6090 | } | 6090 | } |
6091 | } | 6091 | } |