1 files changed, 37 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index b2a92f81..08309f0f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3518,6 +3518,42 @@ clean_up:
         return ret;
 }
 
+static void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
+{
+        struct fifo_gk20a *f = &g->fifo;
+        struct fifo_engine_info_gk20a *gr_info =
+                f->engine_info + ENGINE_GR_GK20A;
+        unsigned long end_jiffies = jiffies +
+                msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
+        u32 ret;
+
+        ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
+        if (ret) {
+                gk20a_err(dev_from_gk20a(g),
+                        "failed to disable gr engine activity\n");
+                return;
+        }
+
+        ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
+        if (ret) {
+                gk20a_err(dev_from_gk20a(g),
+                        "failed to idle graphics\n");
+                goto clean_up;
+        }
+
+        /* update zbc */
+        gk20a_pmu_save_zbc(g, entries);
+
+clean_up:
+        ret = gk20a_fifo_enable_engine_activity(g, gr_info);
+        if (ret) {
+                gk20a_err(dev_from_gk20a(g),
+                        "failed to enable gr engine activity\n");
+        }
+
+        return;
+}
+
 int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
                      struct zbc_entry *zbc_val)
 {
@@ -3607,7 +3643,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
                 /* update zbc for elpg only when new entry is added */
                 entries = max(gr->max_used_color_index,
                                         gr->max_used_depth_index);
-                gk20a_pmu_save_zbc(g, entries);
+                gr_gk20a_pmu_save_zbc(g, entries);
         }
 
         return ret;