diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 788ebf45..4f8006b2 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4679,7 +4679,7 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4679 | nvgpu_cg_init_gr_load_gating_prod(g); | 4679 | nvgpu_cg_init_gr_load_gating_prod(g); |
4680 | 4680 | ||
4681 | /* Disable elcg until it gets enabled later in the init*/ | 4681 | /* Disable elcg until it gets enabled later in the init*/ |
4682 | nvgpu_cg_elcg_disable(g); | 4682 | nvgpu_cg_elcg_disable_no_wait(g); |
4683 | 4683 | ||
4684 | /* enable fifo access */ | 4684 | /* enable fifo access */ |
4685 | gk20a_writel(g, gr_gpfifo_ctl_r(), | 4685 | gk20a_writel(g, gr_gpfifo_ctl_r(), |
@@ -4963,6 +4963,8 @@ int gk20a_init_gr_support(struct gk20a *g) | |||
4963 | 4963 | ||
4964 | nvgpu_log_fn(g, " "); | 4964 | nvgpu_log_fn(g, " "); |
4965 | 4965 | ||
4966 | g->gr.initialized = false; | ||
4967 | |||
4966 | /* this is required before gr_gk20a_init_ctx_state */ | 4968 | /* this is required before gr_gk20a_init_ctx_state */ |
4967 | err = nvgpu_mutex_init(&g->gr.fecs_mutex); | 4969 | err = nvgpu_mutex_init(&g->gr.fecs_mutex); |
4968 | if (err != 0) { | 4970 | if (err != 0) { |
@@ -4999,7 +5001,7 @@ int gk20a_init_gr_support(struct gk20a *g) | |||
4999 | } | 5001 | } |
5000 | } | 5002 | } |
5001 | 5003 | ||
5002 | nvgpu_cg_elcg_enable(g); | 5004 | nvgpu_cg_elcg_enable_no_wait(g); |
5003 | /* GR is inialized, signal possible waiters */ | 5005 | /* GR is inialized, signal possible waiters */ |
5004 | g->gr.initialized = true; | 5006 | g->gr.initialized = true; |
5005 | nvgpu_cond_signal(&g->gr.init_wq); | 5007 | nvgpu_cond_signal(&g->gr.init_wq); |
@@ -5091,6 +5093,8 @@ int gk20a_gr_reset(struct gk20a *g) | |||
5091 | int err; | 5093 | int err; |
5092 | u32 size; | 5094 | u32 size; |
5093 | 5095 | ||
5096 | g->gr.initialized = false; | ||
5097 | |||
5094 | nvgpu_mutex_acquire(&g->gr.fecs_mutex); | 5098 | nvgpu_mutex_acquire(&g->gr.fecs_mutex); |
5095 | 5099 | ||
5096 | err = gk20a_enable_gr_hw(g); | 5100 | err = gk20a_enable_gr_hw(g); |
@@ -5143,7 +5147,11 @@ int gk20a_gr_reset(struct gk20a *g) | |||
5143 | } | 5147 | } |
5144 | 5148 | ||
5145 | nvgpu_cg_init_gr_load_gating_prod(g); | 5149 | nvgpu_cg_init_gr_load_gating_prod(g); |
5146 | nvgpu_cg_elcg_enable(g); | 5150 | nvgpu_cg_elcg_enable_no_wait(g); |
5151 | |||
5152 | /* GR is inialized, signal possible waiters */ | ||
5153 | g->gr.initialized = true; | ||
5154 | nvgpu_cond_signal(&g->gr.init_wq); | ||
5147 | 5155 | ||
5148 | return err; | 5156 | return err; |
5149 | } | 5157 | } |