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path: root/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c32
1 files changed, 10 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index f01b3f37..0cb18665 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -703,12 +703,9 @@ static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g,
703 return ret; 703 return ret;
704} 704}
705 705
706static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c, 706static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c)
707 bool disable_fifo)
708{ 707{
709 struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; 708 struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
710 struct fifo_gk20a *f = &g->fifo;
711 struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A;
712 u32 va_lo, va_hi, va; 709 u32 va_lo, va_hi, va;
713 int ret = 0; 710 int ret = 0;
714 void *ctx_ptr = NULL; 711 void *ctx_ptr = NULL;
@@ -732,30 +729,21 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
732 va_hi = u64_hi32(ch_ctx->zcull_ctx.gpu_va); 729 va_hi = u64_hi32(ch_ctx->zcull_ctx.gpu_va);
733 va = ((va_lo >> 8) & 0x00FFFFFF) | ((va_hi << 24) & 0xFF000000); 730 va = ((va_lo >> 8) & 0x00FFFFFF) | ((va_hi << 24) & 0xFF000000);
734 731
735 if (disable_fifo) { 732 c->g->ops.fifo.disable_channel(c);
736 ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); 733 ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid);
737 if (ret) { 734 if (ret) {
738 gk20a_err(dev_from_gk20a(g), 735 c->g->ops.fifo.enable_channel(c);
739 "failed to disable gr engine activity\n"); 736 gk20a_err(dev_from_gk20a(g),
740 goto clean_up; 737 "failed to disable gr engine activity\n");
741 } 738 goto clean_up;
742 } 739 }
743 740
744 g->ops.mm.fb_flush(g);
745
746 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_o(), 0, 741 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_o(), 0,
747 ch_ctx->zcull_ctx.ctx_sw_mode); 742 ch_ctx->zcull_ctx.ctx_sw_mode);
748 743
749 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_ptr_o(), 0, va); 744 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_ptr_o(), 0, va);
750 745
751 if (disable_fifo) { 746 c->g->ops.fifo.enable_channel(c);
752 ret = gk20a_fifo_enable_engine_activity(g, gr_info);
753 if (ret) {
754 gk20a_err(dev_from_gk20a(g),
755 "failed to enable gr engine activity\n");
756 goto clean_up;
757 }
758 }
759 747
760clean_up: 748clean_up:
761 vunmap(ctx_ptr); 749 vunmap(ctx_ptr);
@@ -3343,7 +3331,7 @@ int gr_gk20a_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
3343 zcull_ctx->gpu_va = zcull_va; 3331 zcull_ctx->gpu_va = zcull_va;
3344 3332
3345 /* TBD: don't disable channel in sw method processing */ 3333 /* TBD: don't disable channel in sw method processing */
3346 return gr_gk20a_ctx_zcull_setup(g, c, true); 3334 return gr_gk20a_ctx_zcull_setup(g, c);
3347} 3335}
3348 3336
3349int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, 3337int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,