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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c273
1 files changed, 273 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
new file mode 100644
index 00000000..d496b7b9
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
@@ -0,0 +1,273 @@
1/*
2 * drivers/video/tegra/host/gk20a/gr_ctx_sim_gk20a.c
3 *
4 * GK20A Graphics Context for Simulation
5 *
6 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27#include "gk20a.h"
28#include "sim_gk20a.h"
29#include "gr_ctx_gk20a.h"
30
31#include <nvgpu/log.h>
32
33int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
34{
35 int err = 0;
36 u32 i, temp;
37
38 gk20a_dbg(gpu_dbg_fn | gpu_dbg_info,
39 "querying grctx info from chiplib");
40
41 g->gr.ctx_vars.dynamic = true;
42 g->gr.netlist = GR_NETLIST_DYNAMIC;
43
44 /* query sizes and counts */
45 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0,
46 &g->gr.ctx_vars.ucode.fecs.inst.count);
47 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0,
48 &g->gr.ctx_vars.ucode.fecs.data.count);
49 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0,
50 &g->gr.ctx_vars.ucode.gpccs.inst.count);
51 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0,
52 &g->gr.ctx_vars.ucode.gpccs.data.count);
53 gk20a_sim_esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp);
54 g->gr.ctx_vars.buffer_size = temp << 2;
55 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0,
56 &g->gr.ctx_vars.sw_bundle_init.count);
57 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0,
58 &g->gr.ctx_vars.sw_method_init.count);
59 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0,
60 &g->gr.ctx_vars.sw_ctx_load.count);
61 gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0,
62 &g->gr.ctx_vars.sw_veid_bundle_init.count);
63
64 gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0,
65 &g->gr.ctx_vars.sw_non_ctx_load.count);
66 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0,
67 &g->gr.ctx_vars.ctxsw_regs.sys.count);
68 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0,
69 &g->gr.ctx_vars.ctxsw_regs.gpc.count);
70 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0,
71 &g->gr.ctx_vars.ctxsw_regs.tpc.count);
72 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0,
73 &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count);
74 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0,
75 &g->gr.ctx_vars.ctxsw_regs.pm_sys.count);
76 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0,
77 &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count);
78 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0,
79 &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count);
80 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
81 &g->gr.ctx_vars.ctxsw_regs.ppc.count);
82 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0,
83 &g->gr.ctx_vars.ctxsw_regs.etpc.count);
84 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
85 &g->gr.ctx_vars.ctxsw_regs.ppc.count);
86
87 err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst);
88 err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.data);
89 err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.inst);
90 err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.data);
91 err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_bundle_init);
92 err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_method_init);
93 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.sw_ctx_load);
94 err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_non_ctx_load);
95 err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_veid_bundle_init);
96 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.sys);
97 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.gpc);
98 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.tpc);
99 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.zcull_gpc);
100 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.ppc);
101 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_sys);
102 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_gpc);
103 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_tpc);
104 err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.etpc);
105
106 if (err)
107 goto fail;
108
109 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++)
110 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS",
111 i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]);
112
113 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++)
114 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS",
115 i, &g->gr.ctx_vars.ucode.fecs.data.l[i]);
116
117 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++)
118 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS",
119 i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]);
120
121 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++)
122 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS",
123 i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]);
124
125 for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) {
126 struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l;
127 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR",
128 i, &l[i].addr);
129 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE",
130 i, &l[i].value);
131 }
132
133 for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) {
134 struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l;
135 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR",
136 i, &l[i].addr);
137 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE",
138 i, &l[i].value);
139 }
140
141 for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) {
142 struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l;
143 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR",
144 i, &l[i].addr);
145 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX",
146 i, &l[i].index);
147 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE",
148 i, &l[i].value);
149 }
150
151 for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) {
152 struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l;
153 gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:REG",
154 i, &l[i].addr);
155 gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE",
156 i, &l[i].value);
157 }
158
159 for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) {
160 struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l;
161
162 gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR",
163 i, &l[i].addr);
164 gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE",
165 i, &l[i].value);
166 }
167
168 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
169 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
170 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",
171 i, &l[i].addr);
172 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX",
173 i, &l[i].index);
174 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE",
175 i, &l[i].value);
176 }
177
178 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) {
179 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l;
180 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR",
181 i, &l[i].addr);
182 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX",
183 i, &l[i].index);
184 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE",
185 i, &l[i].value);
186 }
187
188 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) {
189 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l;
190 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR",
191 i, &l[i].addr);
192 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX",
193 i, &l[i].index);
194 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE",
195 i, &l[i].value);
196 }
197
198 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) {
199 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l;
200 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR",
201 i, &l[i].addr);
202 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX",
203 i, &l[i].index);
204 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE",
205 i, &l[i].value);
206 }
207
208 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) {
209 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l;
210 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR",
211 i, &l[i].addr);
212 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX",
213 i, &l[i].index);
214 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE",
215 i, &l[i].value);
216 }
217
218 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) {
219 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l;
220 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR",
221 i, &l[i].addr);
222 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX",
223 i, &l[i].index);
224 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE",
225 i, &l[i].value);
226 }
227
228 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) {
229 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l;
230 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR",
231 i, &l[i].addr);
232 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX",
233 i, &l[i].index);
234 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE",
235 i, &l[i].value);
236 }
237
238 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) {
239 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l;
240 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR",
241 i, &l[i].addr);
242 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX",
243 i, &l[i].index);
244 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE",
245 i, &l[i].value);
246 }
247
248 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC");
249 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) {
250 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l;
251 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR",
252 i, &l[i].addr);
253 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX",
254 i, &l[i].index);
255 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE",
256 i, &l[i].value);
257 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn,
258 "addr:0x%#08x index:0x%08x value:0x%08x",
259 l[i].addr, l[i].index, l[i].value);
260 }
261
262 g->gr.ctx_vars.valid = true;
263
264 gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0,
265 &g->gr.ctx_vars.regs_base_index);
266
267 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib");
268 return 0;
269fail:
270 nvgpu_err(g, "failed querying grctx info from chiplib");
271 return err;
272
273}
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 13:18:27 -0400