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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h83
1 files changed, 5 insertions, 78 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index ec27ed77..2a9f8a06 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -41,9 +41,10 @@ struct dbg_profiler_object_data;
41 41
42#include "../../../arch/arm/mach-tegra/iomap.h" 42#include "../../../arch/arm/mach-tegra/iomap.h"
43 43
44#include <nvgpu/as.h>
45#include <nvgpu/log.h>
44#include <nvgpu/pramin.h> 46#include <nvgpu/pramin.h>
45#include <nvgpu/acr/nvgpu_acr.h> 47#include <nvgpu/acr/nvgpu_acr.h>
46#include <nvgpu/as.h>
47 48
48#include "clk_gk20a.h" 49#include "clk_gk20a.h"
49#include "ce2_gk20a.h" 50#include "ce2_gk20a.h"
@@ -927,6 +928,9 @@ struct gk20a {
927 bool power_on; 928 bool power_on;
928 bool suspended; 929 bool suspended;
929 930
931 u32 log_mask;
932 u32 log_trace;
933
930 struct rw_semaphore busy_lock; 934 struct rw_semaphore busy_lock;
931 935
932 struct clk_gk20a clk; 936 struct clk_gk20a clk;
@@ -1193,89 +1197,12 @@ struct gk20a_cyclestate_buffer_elem {
1193 u64 data; 1197 u64 data;
1194}; 1198};
1195 1199
1196/* debug accessories */
1197
1198#ifdef CONFIG_DEBUG_FS
1199 /* debug info, default is compiled-in but effectively disabled (0 mask) */
1200 /*e.g: echo 1 > /d/gk20a.0/dbg_mask */
1201 #define GK20A_DEFAULT_DBG_MASK 0
1202#else
1203 /* manually enable and turn it on the mask */
1204 #define GK20A_DEFAULT_DBG_MASK (dbg_info)
1205#endif
1206
1207enum gk20a_dbg_categories {
1208 gpu_dbg_info = BIT(0), /* lightly verbose info */
1209 gpu_dbg_fn = BIT(2), /* fn name tracing */
1210 gpu_dbg_reg = BIT(3), /* register accesses, very verbose */
1211 gpu_dbg_pte = BIT(4), /* gmmu ptes */
1212 gpu_dbg_intr = BIT(5), /* interrupts */
1213 gpu_dbg_pmu = BIT(6), /* gk20a pmu */
1214 gpu_dbg_clk = BIT(7), /* gk20a clk */
1215 gpu_dbg_map = BIT(8), /* mem mappings */
1216 gpu_dbg_gpu_dbg = BIT(9), /* gpu debugger/profiler */
1217 gpu_dbg_cde = BIT(10), /* cde info messages */
1218 gpu_dbg_cde_ctx = BIT(11), /* cde context usage messages */
1219 gpu_dbg_ctxsw = BIT(12), /* ctxsw tracing */
1220 gpu_dbg_sched = BIT(13), /* sched control tracing */
1221 gpu_dbg_map_v = BIT(14), /* verbose mem mappings */
1222 gpu_dbg_sema = BIT(15), /* semaphore debugging */
1223 gpu_dbg_sema_v = BIT(16), /* verbose semaphore debugging */
1224 gpu_dbg_pmu_pstate = BIT(17), /* p state controlled by pmu */
1225 gpu_dbg_xv = BIT(18), /* XVE debugging */
1226 gpu_dbg_shutdown = BIT(19), /* GPU shutdown tracing */
1227 gpu_dbg_kmem = BIT(20), /* Kmem tracking debugging */
1228 gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */
1229};
1230
1231/* operations that will need to be executed on non stall workqueue */ 1200/* operations that will need to be executed on non stall workqueue */
1232enum gk20a_nonstall_ops { 1201enum gk20a_nonstall_ops {
1233 gk20a_nonstall_ops_wakeup_semaphore = BIT(0), /* wake up semaphore */ 1202 gk20a_nonstall_ops_wakeup_semaphore = BIT(0), /* wake up semaphore */
1234 gk20a_nonstall_ops_post_events = BIT(1), 1203 gk20a_nonstall_ops_post_events = BIT(1),
1235}; 1204};
1236 1205
1237extern u32 gk20a_dbg_mask;
1238#ifdef CONFIG_GK20A_TRACE_PRINTK
1239extern u32 gk20a_dbg_ftrace;
1240#define gk20a_dbg(dbg_mask, format, arg...) \
1241do { \
1242 if (unlikely((dbg_mask) & gk20a_dbg_mask)) { \
1243 if (gk20a_dbg_ftrace) \
1244 trace_printk(format "\n", ##arg); \
1245 else \
1246 pr_info("gk20a %s: " format "\n", \
1247 __func__, ##arg); \
1248 } \
1249} while (0)
1250#else
1251#define gk20a_dbg(dbg_mask, format, arg...) \
1252do { \
1253 if (unlikely((dbg_mask) & gk20a_dbg_mask)) { \
1254 pr_info("gk20a %s: " format "\n", \
1255 __func__, ##arg); \
1256 } \
1257} while (0)
1258#endif
1259
1260#define gk20a_err(d, fmt, arg...) \
1261 do { \
1262 if (d) \
1263 dev_err(d, "%s: " fmt "\n", __func__, ##arg); \
1264 } while (0)
1265
1266#define gk20a_warn(d, fmt, arg...) \
1267 do { \
1268 if (d) \
1269 dev_warn(d, "%s: " fmt "\n", __func__, ##arg); \
1270 } while (0)
1271
1272
1273#define gk20a_dbg_fn(fmt, arg...) \
1274 gk20a_dbg(gpu_dbg_fn, fmt, ##arg)
1275
1276#define gk20a_dbg_info(fmt, arg...) \
1277 gk20a_dbg(gpu_dbg_info, fmt, ##arg)
1278
1279void gk20a_init_clk_ops(struct gpu_ops *gops); 1206void gk20a_init_clk_ops(struct gpu_ops *gops);
1280 1207
1281/* register accessors */ 1208/* register accessors */