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-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1474
1 files changed, 1474 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
new file mode 100644
index 00000000..09597bb2
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -0,0 +1,1474 @@
1/*
2 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * GK20A Graphics
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef GK20A_H
25#define GK20A_H
26
27struct gk20a;
28struct fifo_gk20a;
29struct channel_gk20a;
30struct gr_gk20a;
31struct sim_gk20a;
32struct gk20a_ctxsw_ucode_segments;
33struct gk20a_fecs_trace;
34struct gk20a_ctxsw_trace;
35struct acr_desc;
36struct nvgpu_mem_alloc_tracker;
37struct dbg_profiler_object_data;
38struct ecc_gk20a;
39struct gk20a_debug_output;
40struct nvgpu_clk_pll_debug_data;
41struct nvgpu_nvhost_dev;
42struct nvgpu_cpu_time_correlation_sample;
43struct nvgpu_mem_sgt;
44struct nvgpu_warpstate;
45
46#include <nvgpu/lock.h>
47#include <nvgpu/thread.h>
48#include <nvgpu/io.h>
49
50#include <nvgpu/mm.h>
51#include <nvgpu/as.h>
52#include <nvgpu/log.h>
53#include <nvgpu/pramin.h>
54#include <nvgpu/acr/nvgpu_acr.h>
55#include <nvgpu/kref.h>
56#include <nvgpu/falcon.h>
57#include <nvgpu/pmu.h>
58#include <nvgpu/atomic.h>
59#include <nvgpu/barrier.h>
60#include <nvgpu/rwsem.h>
61#include <nvgpu/clk_arb.h>
62
63#include "clk_gk20a.h"
64#include "ce2_gk20a.h"
65#include "fifo_gk20a.h"
66#include "tsg_gk20a.h"
67#include "gr_gk20a.h"
68#include "sim_gk20a.h"
69#include "pmu_gk20a.h"
70#include "priv_ring_gk20a.h"
71#include "therm_gk20a.h"
72#ifdef CONFIG_ARCH_TEGRA_18x_SOC
73#include "clk/clk.h"
74#include "perf/perf.h"
75#include "pmgr/pmgr.h"
76#include "therm/thrm.h"
77#endif
78#include "ecc_gk20a.h"
79
80/* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
81 32 ns is the resolution of ptimer. */
82#define PTIMER_REF_FREQ_HZ 31250000
83
84#ifdef CONFIG_DEBUG_FS
85struct railgate_stats {
86 unsigned long last_rail_gate_start;
87 unsigned long last_rail_gate_complete;
88 unsigned long last_rail_ungate_start;
89 unsigned long last_rail_ungate_complete;
90 unsigned long total_rail_gate_time_ms;
91 unsigned long total_rail_ungate_time_ms;
92 unsigned long railgating_cycle_count;
93};
94#endif
95
96enum gk20a_cbc_op {
97 gk20a_cbc_op_clear,
98 gk20a_cbc_op_clean,
99 gk20a_cbc_op_invalidate,
100};
101
102#define MC_INTR_UNIT_DISABLE false
103#define MC_INTR_UNIT_ENABLE true
104
105#define GPU_LIT_NUM_GPCS 0
106#define GPU_LIT_NUM_PES_PER_GPC 1
107#define GPU_LIT_NUM_ZCULL_BANKS 2
108#define GPU_LIT_NUM_TPC_PER_GPC 3
109#define GPU_LIT_NUM_SM_PER_TPC 4
110#define GPU_LIT_NUM_FBPS 5
111#define GPU_LIT_GPC_BASE 6
112#define GPU_LIT_GPC_STRIDE 7
113#define GPU_LIT_GPC_SHARED_BASE 8
114#define GPU_LIT_TPC_IN_GPC_BASE 9
115#define GPU_LIT_TPC_IN_GPC_STRIDE 10
116#define GPU_LIT_TPC_IN_GPC_SHARED_BASE 11
117#define GPU_LIT_PPC_IN_GPC_BASE 12
118#define GPU_LIT_PPC_IN_GPC_STRIDE 13
119#define GPU_LIT_PPC_IN_GPC_SHARED_BASE 14
120#define GPU_LIT_ROP_BASE 15
121#define GPU_LIT_ROP_STRIDE 16
122#define GPU_LIT_ROP_SHARED_BASE 17
123#define GPU_LIT_HOST_NUM_ENGINES 18
124#define GPU_LIT_HOST_NUM_PBDMA 19
125#define GPU_LIT_LTC_STRIDE 20
126#define GPU_LIT_LTS_STRIDE 21
127#define GPU_LIT_NUM_FBPAS 22
128#define GPU_LIT_FBPA_STRIDE 23
129#define GPU_LIT_FBPA_BASE 24
130#define GPU_LIT_FBPA_SHARED_BASE 25
131#define GPU_LIT_SM_PRI_STRIDE 26
132#define GPU_LIT_SMPC_PRI_BASE 27
133#define GPU_LIT_SMPC_PRI_SHARED_BASE 28
134#define GPU_LIT_SMPC_PRI_UNIQUE_BASE 29
135#define GPU_LIT_SMPC_PRI_STRIDE 30
136#define GPU_LIT_TWOD_CLASS 31
137#define GPU_LIT_THREED_CLASS 32
138#define GPU_LIT_COMPUTE_CLASS 33
139#define GPU_LIT_GPFIFO_CLASS 34
140#define GPU_LIT_I2M_CLASS 35
141#define GPU_LIT_DMA_COPY_CLASS 36
142
143#define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)
144
145enum nvgpu_unit;
146
147enum nvgpu_flush_op;
148/*
149 * gpu_ops should only contain function pointers! Non-function pointer members
150 * should go in struct gk20a or be implemented with the boolean flag API defined
151 * in nvgpu/enabled.h
152 */
153struct gpu_ops {
154 struct {
155 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
156 int (*init_comptags)(struct gk20a *g, struct gr_gk20a *gr);
157 int (*cbc_ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
158 u32 min, u32 max);
159 void (*set_zbc_color_entry)(struct gk20a *g,
160 struct zbc_entry *color_val,
161 u32 index);
162 void (*set_zbc_depth_entry)(struct gk20a *g,
163 struct zbc_entry *depth_val,
164 u32 index);
165 void (*set_zbc_s_entry)(struct gk20a *g,
166 struct zbc_entry *s_val,
167 u32 index);
168 void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
169 void (*set_enabled)(struct gk20a *g, bool enabled);
170 void (*init_fs_state)(struct gk20a *g);
171 void (*isr)(struct gk20a *g);
172 u32 (*cbc_fix_config)(struct gk20a *g, int base);
173 void (*flush)(struct gk20a *g);
174 } ltc;
175 struct {
176 void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);
177 int (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
178 u32 (*get_num_pce)(struct gk20a *g);
179 } ce2;
180 struct {
181 u32 (*get_patch_slots)(struct gk20a *g);
182 int (*init_fs_state)(struct gk20a *g);
183 int (*init_preemption_state)(struct gk20a *g);
184 void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset);
185 void (*bundle_cb_defaults)(struct gk20a *g);
186 void (*cb_size_default)(struct gk20a *g);
187 int (*calc_global_ctx_buffer_size)(struct gk20a *g);
188 void (*commit_global_attrib_cb)(struct gk20a *g,
189 struct channel_ctx_gk20a *ch_ctx,
190 u64 addr, bool patch);
191 void (*commit_global_bundle_cb)(struct gk20a *g,
192 struct channel_ctx_gk20a *ch_ctx,
193 u64 addr, u64 size, bool patch);
194 int (*commit_global_cb_manager)(struct gk20a *g,
195 struct channel_gk20a *ch,
196 bool patch);
197 void (*commit_global_pagepool)(struct gk20a *g,
198 struct channel_ctx_gk20a *ch_ctx,
199 u64 addr, u32 size, bool patch);
200 void (*init_gpc_mmu)(struct gk20a *g);
201 int (*handle_sw_method)(struct gk20a *g, u32 addr,
202 u32 class_num, u32 offset, u32 data);
203 void (*set_alpha_circular_buffer_size)(struct gk20a *g,
204 u32 data);
205 void (*set_circular_buffer_size)(struct gk20a *g, u32 data);
206 void (*set_bes_crop_debug3)(struct gk20a *g, u32 data);
207 void (*enable_hww_exceptions)(struct gk20a *g);
208 bool (*is_valid_class)(struct gk20a *g, u32 class_num);
209 bool (*is_valid_gfx_class)(struct gk20a *g, u32 class_num);
210 bool (*is_valid_compute_class)(struct gk20a *g, u32 class_num);
211 void (*get_sm_dsm_perf_regs)(struct gk20a *g,
212 u32 *num_sm_dsm_perf_regs,
213 u32 **sm_dsm_perf_regs,
214 u32 *perf_register_stride);
215 void (*get_sm_dsm_perf_ctrl_regs)(struct gk20a *g,
216 u32 *num_sm_dsm_perf_regs,
217 u32 **sm_dsm_perf_regs,
218 u32 *perf_register_stride);
219 void (*get_ovr_perf_regs)(struct gk20a *g,
220 u32 *num_ovr_perf_regs,
221 u32 **ovr_perf_regsr);
222 void (*set_hww_esr_report_mask)(struct gk20a *g);
223 int (*setup_alpha_beta_tables)(struct gk20a *g,
224 struct gr_gk20a *gr);
225 int (*falcon_load_ucode)(struct gk20a *g,
226 u64 addr_base,
227 struct gk20a_ctxsw_ucode_segments *segments,
228 u32 reg_offset);
229 int (*load_ctxsw_ucode)(struct gk20a *g);
230 u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
231 void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
232 void (*free_channel_ctx)(struct channel_gk20a *c, bool is_tsg);
233 int (*alloc_obj_ctx)(struct channel_gk20a *c,
234 u32 class_num, u32 flags);
235 int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr,
236 struct channel_gk20a *c, u64 zcull_va,
237 u32 mode);
238 int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr,
239 struct gr_zcull_info *zcull_params);
240 int (*decode_egpc_addr)(struct gk20a *g,
241 u32 addr, int *addr_type,
242 u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags);
243 void (*egpc_etpc_priv_addr_table)(struct gk20a *g, u32 addr,
244 u32 gpc, u32 broadcast_flags, u32 *priv_addr_table,
245 u32 *priv_addr_table_index);
246 bool (*is_tpc_addr)(struct gk20a *g, u32 addr);
247 bool (*is_egpc_addr)(struct gk20a *g, u32 addr);
248 bool (*is_etpc_addr)(struct gk20a *g, u32 addr);
249 void (*get_egpc_etpc_num)(struct gk20a *g, u32 addr,
250 u32 *gpc_num, u32 *tpc_num);
251 u32 (*get_tpc_num)(struct gk20a *g, u32 addr);
252 u32 (*get_egpc_base)(struct gk20a *g);
253 bool (*is_ltcs_ltss_addr)(struct gk20a *g, u32 addr);
254 bool (*is_ltcn_ltss_addr)(struct gk20a *g, u32 addr);
255 bool (*get_lts_in_ltc_shared_base)(void);
256 void (*split_lts_broadcast_addr)(struct gk20a *g, u32 addr,
257 u32 *priv_addr_table,
258 u32 *priv_addr_table_index);
259 void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr,
260 u32 *priv_addr_table,
261 u32 *priv_addr_table_index);
262 void (*detect_sm_arch)(struct gk20a *g);
263 int (*add_zbc_color)(struct gk20a *g, struct gr_gk20a *gr,
264 struct zbc_entry *color_val, u32 index);
265 int (*add_zbc_depth)(struct gk20a *g, struct gr_gk20a *gr,
266 struct zbc_entry *depth_val, u32 index);
267 int (*add_zbc_s)(struct gk20a *g, struct gr_gk20a *gr,
268 struct zbc_entry *s_val, u32 index);
269 int (*zbc_set_table)(struct gk20a *g, struct gr_gk20a *gr,
270 struct zbc_entry *zbc_val);
271 int (*zbc_query_table)(struct gk20a *g, struct gr_gk20a *gr,
272 struct zbc_query_params *query_params);
273 int (*zbc_s_query_table)(struct gk20a *g, struct gr_gk20a *gr,
274 struct zbc_query_params *query_params);
275 int (*load_zbc_s_default_tbl)(struct gk20a *g,
276 struct gr_gk20a *gr);
277 int (*load_zbc_s_tbl)(struct gk20a *g,
278 struct gr_gk20a *gr);
279 void (*pmu_save_zbc)(struct gk20a *g, u32 entries);
280 int (*add_zbc)(struct gk20a *g, struct gr_gk20a *gr,
281 struct zbc_entry *zbc_val);
282 bool (*add_zbc_type_s)(struct gk20a *g, struct gr_gk20a *gr,
283 struct zbc_entry *zbc_val, int *ret_val);
284 u32 (*pagepool_default_size)(struct gk20a *g);
285 int (*init_ctx_state)(struct gk20a *g);
286 int (*alloc_gr_ctx)(struct gk20a *g,
287 struct gr_ctx_desc **__gr_ctx, struct vm_gk20a *vm,
288 u32 class, u32 padding);
289 void (*free_gr_ctx)(struct gk20a *g,
290 struct vm_gk20a *vm,
291 struct gr_ctx_desc *gr_ctx);
292 void (*update_ctxsw_preemption_mode)(struct gk20a *g,
293 struct channel_ctx_gk20a *ch_ctx,
294 struct nvgpu_mem *mem);
295 int (*update_smpc_ctxsw_mode)(struct gk20a *g,
296 struct channel_gk20a *c,
297 bool enable);
298 int (*update_hwpm_ctxsw_mode)(struct gk20a *g,
299 struct channel_gk20a *c,
300 bool enable);
301 int (*dump_gr_regs)(struct gk20a *g,
302 struct gk20a_debug_output *o);
303 int (*update_pc_sampling)(struct channel_gk20a *ch,
304 bool enable);
305 u32 (*get_max_fbps_count)(struct gk20a *g);
306 u32 (*get_fbp_en_mask)(struct gk20a *g);
307 u32 (*get_max_ltc_per_fbp)(struct gk20a *g);
308 u32 (*get_max_lts_per_ltc)(struct gk20a *g);
309 u32* (*get_rop_l2_en_mask)(struct gk20a *g);
310 void (*init_sm_dsm_reg_info)(void);
311 void (*init_ovr_sm_dsm_perf)(void);
312 int (*wait_empty)(struct gk20a *g, unsigned long duration_ms,
313 u32 expect_delay);
314 void (*init_cyclestats)(struct gk20a *g);
315 void (*enable_cde_in_fecs)(struct gk20a *g,
316 struct nvgpu_mem *mem);
317 int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch,
318 u64 sms, bool enable);
319 void (*bpt_reg_info)(struct gk20a *g,
320 struct nvgpu_warpstate *w_state);
321 void (*get_access_map)(struct gk20a *g,
322 u32 **whitelist, int *num_entries);
323 int (*handle_fecs_error)(struct gk20a *g,
324 struct channel_gk20a *ch,
325 struct gr_gk20a_isr_data *isr_data);
326 int (*pre_process_sm_exception)(struct gk20a *g,
327 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
328 bool sm_debugger_attached,
329 struct channel_gk20a *fault_ch,
330 bool *early_exit, bool *ignore_debugger);
331 u32 (*get_sm_hww_warp_esr)(struct gk20a *g,
332 u32 gpc, u32 tpc, u32 sm);
333 u32 (*get_sm_hww_global_esr)(struct gk20a *g,
334 u32 gpc, u32 tpc, u32 sm);
335 u32 (*get_sm_no_lock_down_hww_global_esr_mask)(struct gk20a *g);
336 int (*lock_down_sm)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
337 u32 global_esr_mask, bool check_errors);
338 int (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc,
339 u32 sm, u32 global_esr_mask, bool check_errors);
340 void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
341 u32 global_esr);
342 void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc,
343 u32 *esr_sm_sel);
344 int (*handle_tpc_sm_ecc_exception)(struct gk20a *g,
345 u32 gpc, u32 tpc,
346 bool *post_event, struct channel_gk20a *fault_ch,
347 u32 *hww_global_esr);
348 int (*handle_sm_exception)(struct gk20a *g,
349 u32 gpc, u32 tpc, u32 sm,
350 bool *post_event, struct channel_gk20a *fault_ch,
351 u32 *hww_global_esr);
352 int (*handle_gcc_exception)(struct gk20a *g, u32 gpc, u32 tpc,
353 bool *post_event, struct channel_gk20a *fault_ch,
354 u32 *hww_global_esr);
355 int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc,
356 bool *post_event);
357 int (*handle_tpc_mpc_exception)(struct gk20a *g,
358 u32 gpc, u32 tpc, bool *post_event);
359 int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc,
360 u32 gpc_exception);
361 int (*handle_gpc_gpcmmu_exception)(struct gk20a *g, u32 gpc,
362 u32 gpc_exception);
363 void (*enable_gpc_exceptions)(struct gk20a *g);
364 void (*enable_exceptions)(struct gk20a *g);
365 void (*create_gr_sysfs)(struct gk20a *g);
366 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
367 int (*record_sm_error_state)(struct gk20a *g,
368 u32 gpc, u32 tpc);
369 int (*update_sm_error_state)(struct gk20a *g,
370 struct channel_gk20a *ch, u32 sm_id,
371 struct nvgpu_gr_sm_error_state *sm_error_state);
372 int (*clear_sm_error_state)(struct gk20a *g,
373 struct channel_gk20a *ch, u32 sm_id);
374 int (*suspend_contexts)(struct gk20a *g,
375 struct dbg_session_gk20a *dbg_s,
376 int *ctx_resident_ch_fd);
377 int (*resume_contexts)(struct gk20a *g,
378 struct dbg_session_gk20a *dbg_s,
379 int *ctx_resident_ch_fd);
380 int (*set_preemption_mode)(struct channel_gk20a *ch,
381 u32 graphics_preempt_mode,
382 u32 compute_preempt_mode);
383 int (*get_preemption_mode_flags)(struct gk20a *g,
384 struct nvgpu_preemption_modes_rec *preemption_modes_rec);
385 int (*set_ctxsw_preemption_mode)(struct gk20a *g,
386 struct gr_ctx_desc *gr_ctx,
387 struct vm_gk20a *vm, u32 class,
388 u32 graphics_preempt_mode,
389 u32 compute_preempt_mode);
390 int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost);
391 void (*update_boosted_ctx)(struct gk20a *g,
392 struct nvgpu_mem *mem,
393 struct gr_ctx_desc *gr_ctx);
394 void (*init_sm_id_table)(struct gk20a *g);
395 int (*load_smid_config)(struct gk20a *g);
396 void (*program_sm_id_numbering)(struct gk20a *g,
397 u32 gpc, u32 tpc, u32 smid);
398 void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc);
399 int (*setup_rop_mapping)(struct gk20a *g, struct gr_gk20a *gr);
400 int (*init_sw_veid_bundle)(struct gk20a *g);
401 void (*program_zcull_mapping)(struct gk20a *g,
402 u32 zcull_alloc_num, u32 *zcull_map_tiles);
403 int (*commit_global_timeslice)(struct gk20a *g,
404 struct channel_gk20a *c);
405 int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va);
406 void (*write_zcull_ptr)(struct gk20a *g,
407 struct nvgpu_mem *mem, u64 gpu_va);
408 void (*write_pm_ptr)(struct gk20a *g,
409 struct nvgpu_mem *mem, u64 gpu_va);
410 void (*set_preemption_buffer_va)(struct gk20a *g,
411 struct nvgpu_mem *mem, u64 gpu_va);
412 void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
413 void (*load_tpc_mask)(struct gk20a *g);
414 int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch);
415 int (*trigger_suspend)(struct gk20a *g);
416 int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state);
417 int (*resume_from_pause)(struct gk20a *g);
418 int (*clear_sm_errors)(struct gk20a *g);
419 u32 (*tpc_enabled_exceptions)(struct gk20a *g);
420 int (*set_czf_bypass)(struct gk20a *g,
421 struct channel_gk20a *ch);
422 void (*init_czf_bypass)(struct gk20a *g);
423 bool (*sm_debugger_attached)(struct gk20a *g);
424 void (*suspend_single_sm)(struct gk20a *g,
425 u32 gpc, u32 tpc, u32 sm,
426 u32 global_esr_mask, bool check_errors);
427 void (*suspend_all_sms)(struct gk20a *g,
428 u32 global_esr_mask, bool check_errors);
429 void (*resume_single_sm)(struct gk20a *g,
430 u32 gpc, u32 tpc, u32 sm);
431 void (*resume_all_sms)(struct gk20a *g);
432 void (*disable_rd_coalesce)(struct gk20a *g);
433 void (*init_ctxsw_hdr_data)(struct gk20a *g,
434 struct nvgpu_mem *mem);
435
436 } gr;
437 struct {
438 void (*init_hw)(struct gk20a *g);
439 void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
440 void (*init_fs_state)(struct gk20a *g);
441 void (*reset)(struct gk20a *g);
442 void (*init_uncompressed_kind_map)(struct gk20a *g);
443 void (*init_kind_attr)(struct gk20a *g);
444 void (*set_mmu_page_size)(struct gk20a *g);
445 bool (*set_use_full_comp_tag_line)(struct gk20a *g);
446 unsigned int (*compression_page_size)(struct gk20a *g);
447 unsigned int (*compressible_page_size)(struct gk20a *g);
448 void (*dump_vpr_wpr_info)(struct gk20a *g);
449 int (*vpr_info_fetch)(struct gk20a *g);
450 void (*read_wpr_info)(struct gk20a *g,
451 struct wpr_carveout_info *inf);
452 bool (*is_debug_mode_enabled)(struct gk20a *g);
453 void (*set_debug_mode)(struct gk20a *g, bool enable);
454 void (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb);
455 void (*hub_isr)(struct gk20a *g);
456 int (*mem_unlock)(struct gk20a *g);
457 } fb;
458 struct {
459 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
460 void (*slcg_ce2_load_gating_prod)(struct gk20a *g, bool prod);
461 void (*slcg_chiplet_load_gating_prod)(struct gk20a *g, bool prod);
462 void (*slcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod);
463 void (*slcg_fb_load_gating_prod)(struct gk20a *g, bool prod);
464 void (*slcg_fifo_load_gating_prod)(struct gk20a *g, bool prod);
465 void (*slcg_gr_load_gating_prod)(struct gk20a *g, bool prod);
466 void (*slcg_ltc_load_gating_prod)(struct gk20a *g, bool prod);
467 void (*slcg_perf_load_gating_prod)(struct gk20a *g, bool prod);
468 void (*slcg_priring_load_gating_prod)(struct gk20a *g, bool prod);
469 void (*slcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
470 void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod);
471 void (*slcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
472 void (*blcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
473 void (*blcg_ce_load_gating_prod)(struct gk20a *g, bool prod);
474 void (*blcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod);
475 void (*blcg_fb_load_gating_prod)(struct gk20a *g, bool prod);
476 void (*blcg_fifo_load_gating_prod)(struct gk20a *g, bool prod);
477 void (*blcg_gr_load_gating_prod)(struct gk20a *g, bool prod);
478 void (*blcg_ltc_load_gating_prod)(struct gk20a *g, bool prod);
479 void (*blcg_pwr_csb_load_gating_prod)(struct gk20a *g, bool prod);
480 void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
481 void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
482 void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod);
483 } clock_gating;
484 struct {
485 int (*init_fifo_setup_hw)(struct gk20a *g);
486 void (*bind_channel)(struct channel_gk20a *ch_gk20a);
487 void (*unbind_channel)(struct channel_gk20a *ch_gk20a);
488 void (*disable_channel)(struct channel_gk20a *ch);
489 void (*enable_channel)(struct channel_gk20a *ch);
490 int (*alloc_inst)(struct gk20a *g, struct channel_gk20a *ch);
491 void (*free_inst)(struct gk20a *g, struct channel_gk20a *ch);
492 int (*setup_ramfc)(struct channel_gk20a *c, u64 gpfifo_base,
493 u32 gpfifo_entries,
494 unsigned long acquire_timeout,
495 u32 flags);
496 int (*resetup_ramfc)(struct channel_gk20a *c);
497 int (*preempt_channel)(struct gk20a *g, u32 chid);
498 int (*preempt_tsg)(struct gk20a *g, u32 tsgid);
499 int (*enable_tsg)(struct tsg_gk20a *tsg);
500 int (*disable_tsg)(struct tsg_gk20a *tsg);
501 int (*tsg_verify_channel_status)(struct channel_gk20a *ch);
502 void (*tsg_verify_status_ctx_reload)(struct channel_gk20a *ch);
503 void (*tsg_verify_status_faulted)(struct channel_gk20a *ch);
504 int (*reschedule_runlist)(struct gk20a *g, u32 runlist_id);
505 int (*update_runlist)(struct gk20a *g, u32 runlist_id,
506 u32 chid, bool add,
507 bool wait_for_finish);
508 void (*trigger_mmu_fault)(struct gk20a *g,
509 unsigned long engine_ids);
510 void (*get_mmu_fault_info)(struct gk20a *g, u32 mmu_fault_id,
511 struct mmu_fault_info *mmfault);
512 void (*apply_pb_timeout)(struct gk20a *g);
513 int (*wait_engine_idle)(struct gk20a *g);
514 u32 (*get_num_fifos)(struct gk20a *g);
515 u32 (*get_pbdma_signature)(struct gk20a *g);
516 int (*set_runlist_interleave)(struct gk20a *g, u32 id,
517 bool is_tsg, u32 runlist_id,
518 u32 new_level);
519 int (*channel_set_timeslice)(struct channel_gk20a *ch,
520 u32 timeslice);
521 int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice);
522 u32 (*default_timeslice_us)(struct gk20a *);
523 int (*force_reset_ch)(struct channel_gk20a *ch,
524 u32 err_code, bool verbose);
525 int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type,
526 u32 *inst_id);
527 void (*device_info_data_parse)(struct gk20a *g,
528 u32 table_entry, u32 *inst_id,
529 u32 *pri_base, u32 *fault_id);
530 u32 (*device_info_fault_id)(u32 table_entry);
531 int (*tsg_bind_channel)(struct tsg_gk20a *tsg,
532 struct channel_gk20a *ch);
533 int (*tsg_unbind_channel)(struct channel_gk20a *ch);
534 int (*tsg_open)(struct tsg_gk20a *tsg);
535 u32 (*eng_runlist_base_size)(void);
536 int (*init_engine_info)(struct fifo_gk20a *f);
537 u32 (*runlist_entry_size)(void);
538 void (*get_tsg_runlist_entry)(struct tsg_gk20a *tsg,
539 u32 *runlist);
540 void (*get_ch_runlist_entry)(struct channel_gk20a *ch,
541 u32 *runlist);
542 u32 (*userd_gp_get)(struct gk20a *g, struct channel_gk20a *ch);
543 void (*userd_gp_put)(struct gk20a *g, struct channel_gk20a *ch);
544 u64 (*userd_pb_get)(struct gk20a *g, struct channel_gk20a *ch);
545 void (*free_channel_ctx_header)(struct channel_gk20a *ch);
546 bool (*is_fault_engine_subid_gpc)(struct gk20a *g,
547 u32 engine_subid);
548 void (*dump_pbdma_status)(struct gk20a *g,
549 struct gk20a_debug_output *o);
550 void (*dump_eng_status)(struct gk20a *g,
551 struct gk20a_debug_output *o);
552 void (*dump_channel_status_ramfc)(struct gk20a *g,
553 struct gk20a_debug_output *o, u32 chid,
554 struct ch_state *ch_state);
555 u32 (*intr_0_error_mask)(struct gk20a *g);
556 int (*is_preempt_pending)(struct gk20a *g, u32 id,
557 unsigned int id_type, unsigned int timeout_rc_type);
558 int (*preempt_ch_tsg)(struct gk20a *g, u32 id,
559 unsigned int id_type, unsigned int timeout_rc_type);
560 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
561 int (*reset_enable_hw)(struct gk20a *g);
562 int (*setup_userd)(struct channel_gk20a *c);
563 u32 (*pbdma_acquire_val)(u64 timeout);
564 void (*teardown_ch_tsg)(struct gk20a *g, u32 act_eng_bitmask,
565 u32 id, unsigned int id_type, unsigned int rc_type,
566 struct mmu_fault_info *mmfault);
567 bool (*handle_sched_error)(struct gk20a *g);
568 bool (*handle_ctxsw_timeout)(struct gk20a *g, u32 fifo_intr);
569 unsigned int (*handle_pbdma_intr_0)(struct gk20a *g,
570 u32 pbdma_id, u32 pbdma_intr_0,
571 u32 *handled, u32 *error_notifier);
572 unsigned int (*handle_pbdma_intr_1)(struct gk20a *g,
573 u32 pbdma_id, u32 pbdma_intr_1,
574 u32 *handled, u32 *error_notifier);
575 void (*init_eng_method_buffers)(struct gk20a *g,
576 struct tsg_gk20a *tsg);
577 void (*deinit_eng_method_buffers)(struct gk20a *g,
578 struct tsg_gk20a *tsg);
579 u32 (*get_preempt_timeout)(struct gk20a *g);
580#ifdef CONFIG_TEGRA_GK20A_NVHOST
581 int (*alloc_syncpt_buf)(struct channel_gk20a *c,
582 u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
583 void (*free_syncpt_buf)(struct channel_gk20a *c,
584 struct nvgpu_mem *syncpt_buf);
585 void (*add_syncpt_wait_cmd)(struct gk20a *g,
586 struct priv_cmd_entry *cmd, u32 off,
587 u32 id, u32 thresh, u64 gpu_va);
588 u32 (*get_syncpt_wait_cmd_size)(void);
589 void (*add_syncpt_incr_cmd)(struct gk20a *g,
590 bool wfi_cmd, struct priv_cmd_entry *cmd,
591 u32 id, u64 gpu_va);
592 u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd);
593#endif
594 } fifo;
595 struct pmu_v {
596 u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);
597 void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu,
598 u32 freq);
599 void (*set_pmu_cmdline_args_trace_size)(struct nvgpu_pmu *pmu,
600 u32 size);
601 void (*set_pmu_cmdline_args_trace_dma_base)(
602 struct nvgpu_pmu *pmu);
603 void (*set_pmu_cmdline_args_trace_dma_idx)(
604 struct nvgpu_pmu *pmu, u32 idx);
605 void * (*get_pmu_cmdline_args_ptr)(struct nvgpu_pmu *pmu);
606 u32 (*get_pmu_allocation_struct_size)(struct nvgpu_pmu *pmu);
607 void (*set_pmu_allocation_ptr)(struct nvgpu_pmu *pmu,
608 void **pmu_alloc_ptr, void *assign_ptr);
609 void (*pmu_allocation_set_dmem_size)(struct nvgpu_pmu *pmu,
610 void *pmu_alloc_ptr, u16 size);
611 u16 (*pmu_allocation_get_dmem_size)(struct nvgpu_pmu *pmu,
612 void *pmu_alloc_ptr);
613 u32 (*pmu_allocation_get_dmem_offset)(struct nvgpu_pmu *pmu,
614 void *pmu_alloc_ptr);
615 u32 * (*pmu_allocation_get_dmem_offset_addr)(
616 struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
617 void (*pmu_allocation_set_dmem_offset)(struct nvgpu_pmu *pmu,
618 void *pmu_alloc_ptr, u32 offset);
619 void * (*pmu_allocation_get_fb_addr)(
620 struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
621 u32 (*pmu_allocation_get_fb_size)(
622 struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
623 void (*get_pmu_init_msg_pmu_queue_params)(
624 struct pmu_queue *queue, u32 id,
625 void *pmu_init_msg);
626 void *(*get_pmu_msg_pmu_init_msg_ptr)(
627 struct pmu_init_msg *init);
628 u16 (*get_pmu_init_msg_pmu_sw_mg_off)(
629 union pmu_init_msg_pmu *init_msg);
630 u16 (*get_pmu_init_msg_pmu_sw_mg_size)(
631 union pmu_init_msg_pmu *init_msg);
632 u32 (*get_pmu_perfmon_cmd_start_size)(void);
633 int (*get_perfmon_cmd_start_offsetofvar)(
634 enum pmu_perfmon_cmd_start_fields field);
635 void (*perfmon_start_set_cmd_type)(struct pmu_perfmon_cmd *pc,
636 u8 value);
637 void (*perfmon_start_set_group_id)(struct pmu_perfmon_cmd *pc,
638 u8 value);
639 void (*perfmon_start_set_state_id)(struct pmu_perfmon_cmd *pc,
640 u8 value);
641 void (*perfmon_start_set_flags)(struct pmu_perfmon_cmd *pc,
642 u8 value);
643 u8 (*perfmon_start_get_flags)(struct pmu_perfmon_cmd *pc);
644 u32 (*get_pmu_perfmon_cmd_init_size)(void);
645 int (*get_perfmon_cmd_init_offsetofvar)(
646 enum pmu_perfmon_cmd_start_fields field);
647 void (*perfmon_cmd_init_set_sample_buffer)(
648 struct pmu_perfmon_cmd *pc, u16 value);
649 void (*perfmon_cmd_init_set_dec_cnt)(
650 struct pmu_perfmon_cmd *pc, u8 value);
651 void (*perfmon_cmd_init_set_base_cnt_id)(
652 struct pmu_perfmon_cmd *pc, u8 value);
653 void (*perfmon_cmd_init_set_samp_period_us)(
654 struct pmu_perfmon_cmd *pc, u32 value);
655 void (*perfmon_cmd_init_set_num_cnt)(struct pmu_perfmon_cmd *pc,
656 u8 value);
657 void (*perfmon_cmd_init_set_mov_avg)(struct pmu_perfmon_cmd *pc,
658 u8 value);
659 void *(*get_pmu_seq_in_a_ptr)(
660 struct pmu_sequence *seq);
661 void *(*get_pmu_seq_out_a_ptr)(
662 struct pmu_sequence *seq);
663 void (*set_pmu_cmdline_args_secure_mode)(struct nvgpu_pmu *pmu,
664 u32 val);
665 u32 (*get_perfmon_cntr_sz)(struct nvgpu_pmu *pmu);
666 void * (*get_perfmon_cntr_ptr)(struct nvgpu_pmu *pmu);
667 void (*set_perfmon_cntr_ut)(struct nvgpu_pmu *pmu, u16 ut);
668 void (*set_perfmon_cntr_lt)(struct nvgpu_pmu *pmu, u16 lt);
669 void (*set_perfmon_cntr_valid)(struct nvgpu_pmu *pmu, u8 val);
670 void (*set_perfmon_cntr_index)(struct nvgpu_pmu *pmu, u8 val);
671 void (*set_perfmon_cntr_group_id)(struct nvgpu_pmu *pmu,
672 u8 gid);
673
674 u8 (*pg_cmd_eng_buf_load_size)(struct pmu_pg_cmd *pg);
675 void (*pg_cmd_eng_buf_load_set_cmd_type)(struct pmu_pg_cmd *pg,
676 u8 value);
677 void (*pg_cmd_eng_buf_load_set_engine_id)(struct pmu_pg_cmd *pg,
678 u8 value);
679 void (*pg_cmd_eng_buf_load_set_buf_idx)(struct pmu_pg_cmd *pg,
680 u8 value);
681 void (*pg_cmd_eng_buf_load_set_pad)(struct pmu_pg_cmd *pg,
682 u8 value);
683 void (*pg_cmd_eng_buf_load_set_buf_size)(struct pmu_pg_cmd *pg,
684 u16 value);
685 void (*pg_cmd_eng_buf_load_set_dma_base)(struct pmu_pg_cmd *pg,
686 u32 value);
687 void (*pg_cmd_eng_buf_load_set_dma_offset)(struct pmu_pg_cmd *pg,
688 u8 value);
689 void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg,
690 u8 value);
691 } pmu_ver;
692 struct {
693 int (*get_netlist_name)(struct gk20a *g, int index, char *name);
694 bool (*is_fw_defined)(void);
695 } gr_ctx;
696#ifdef CONFIG_GK20A_CTXSW_TRACE
697 /*
698 * Currently only supported on Linux due to the extremely tight
699 * integration with Linux device driver structure (in particular
700 * mmap).
701 */
702 struct {
703 int (*init)(struct gk20a *g);
704 int (*max_entries)(struct gk20a *,
705 struct nvgpu_ctxsw_trace_filter *filter);
706 int (*flush)(struct gk20a *g);
707 int (*poll)(struct gk20a *g);
708 int (*enable)(struct gk20a *g);
709 int (*disable)(struct gk20a *g);
710 bool (*is_enabled)(struct gk20a *g);
711 int (*reset)(struct gk20a *g);
712 int (*bind_channel)(struct gk20a *g, struct channel_gk20a *ch);
713 int (*unbind_channel)(struct gk20a *g,
714 struct channel_gk20a *ch);
715 int (*deinit)(struct gk20a *g);
716 int (*alloc_user_buffer)(struct gk20a *g,
717 void **buf, size_t *size);
718 int (*free_user_buffer)(struct gk20a *g);
719 int (*mmap_user_buffer)(struct gk20a *g,
720 struct vm_area_struct *vma);
721 int (*set_filter)(struct gk20a *g,
722 struct nvgpu_ctxsw_trace_filter *filter);
723 } fecs_trace;
724#endif
725 struct {
726 bool (*support_sparse)(struct gk20a *g);
727 u64 (*gmmu_map)(struct vm_gk20a *vm,
728 u64 map_offset,
729 struct nvgpu_sgt *sgt,
730 u64 buffer_offset,
731 u64 size,
732 int pgsz_idx,
733 u8 kind_v,
734 u32 ctag_offset,
735 u32 flags,
736 int rw_flag,
737 bool clear_ctags,
738 bool sparse,
739 bool priv,
740 struct vm_gk20a_mapping_batch *batch,
741 enum nvgpu_aperture aperture);
742 void (*gmmu_unmap)(struct vm_gk20a *vm,
743 u64 vaddr,
744 u64 size,
745 int pgsz_idx,
746 bool va_allocated,
747 int rw_flag,
748 bool sparse,
749 struct vm_gk20a_mapping_batch *batch);
750 int (*vm_bind_channel)(struct gk20a_as_share *as_share,
751 struct channel_gk20a *ch);
752 int (*fb_flush)(struct gk20a *g);
753 void (*l2_invalidate)(struct gk20a *g);
754 void (*l2_flush)(struct gk20a *g, bool invalidate);
755 void (*cbc_clean)(struct gk20a *g);
756 void (*set_big_page_size)(struct gk20a *g,
757 struct nvgpu_mem *mem, int size);
758 u32 (*get_big_page_sizes)(void);
759 u32 (*get_default_big_page_size)(void);
760 u32 (*get_iommu_bit)(struct gk20a *g);
761 int (*init_mm_setup_hw)(struct gk20a *g);
762 bool (*is_bar1_supported)(struct gk20a *g);
763 int (*init_bar2_vm)(struct gk20a *g);
764 int (*init_bar2_mm_hw_setup)(struct gk20a *g);
765 void (*remove_bar2_vm)(struct gk20a *g);
766 const struct gk20a_mmu_level *
767 (*get_mmu_levels)(struct gk20a *g, u32 big_page_size);
768 void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block,
769 struct vm_gk20a *vm);
770 u64 (*gpu_phys_addr)(struct gk20a *g,
771 struct nvgpu_gmmu_attrs *attrs, u64 phys);
772 size_t (*get_vidmem_size)(struct gk20a *g);
773 int (*alloc_inst_block)(struct gk20a *g,
774 struct nvgpu_mem *inst_block);
775 void (*init_inst_block)(struct nvgpu_mem *inst_block,
776 struct vm_gk20a *vm, u32 big_page_size);
777 bool (*mmu_fault_pending)(struct gk20a *g);
778 void (*fault_info_mem_destroy)(struct gk20a *g);
779 u32 (*get_kind_invalid)(void);
780 u32 (*get_kind_pitch)(void);
781 u32 (*get_flush_retries)(struct gk20a *g,
782 enum nvgpu_flush_op op);
783 } mm;
784 /*
785 * This function is called to allocate secure memory (memory
786 * that the CPU cannot see). The function should fill the
787 * context buffer descriptor (especially fields destroy, sgt,
788 * size).
789 */
790 int (*secure_alloc)(struct gk20a *g,
791 struct gr_ctx_buffer_desc *desc,
792 size_t size);
793 struct {
794 u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem,
795 struct nvgpu_sgt *sgt, void *sgl, u32 w);
796 void (*exit)(struct gk20a *g, struct nvgpu_mem *mem,
797 void *sgl);
798 u32 (*data032_r)(u32 i);
799 } pramin;
800 struct {
801 int (*init_therm_setup_hw)(struct gk20a *g);
802 int (*elcg_init_idle_filters)(struct gk20a *g);
803#ifdef CONFIG_DEBUG_FS
804 void (*therm_debugfs_init)(struct gk20a *g);
805#endif
806 int (*get_internal_sensor_curr_temp)(struct gk20a *g, u32 *temp_f24_8);
807 void (*get_internal_sensor_limits)(s32 *max_24_8,
808 s32 *min_24_8);
809 u32 (*configure_therm_alert)(struct gk20a *g, s32 curr_warn_temp);
810 } therm;
811 struct {
812 bool (*is_pmu_supported)(struct gk20a *g);
813 int (*prepare_ucode)(struct gk20a *g);
814 int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g);
815 int (*pmu_nsbootstrap)(struct nvgpu_pmu *pmu);
816 int (*pmu_setup_elpg)(struct gk20a *g);
817 u32 (*pmu_get_queue_head)(u32 i);
818 u32 (*pmu_get_queue_head_size)(void);
819 u32 (*pmu_get_queue_tail_size)(void);
820 u32 (*pmu_get_queue_tail)(u32 i);
821 int (*pmu_queue_head)(struct nvgpu_pmu *pmu,
822 struct pmu_queue *queue, u32 *head, bool set);
823 int (*pmu_queue_tail)(struct nvgpu_pmu *pmu,
824 struct pmu_queue *queue, u32 *tail, bool set);
825 void (*pmu_msgq_tail)(struct nvgpu_pmu *pmu,
826 u32 *tail, bool set);
827 u32 (*pmu_mutex_size)(void);
828 int (*pmu_mutex_acquire)(struct nvgpu_pmu *pmu,
829 u32 id, u32 *token);
830 int (*pmu_mutex_release)(struct nvgpu_pmu *pmu,
831 u32 id, u32 *token);
832 int (*init_wpr_region)(struct gk20a *g);
833 int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask);
834 void (*write_dmatrfbase)(struct gk20a *g, u32 addr);
835 void (*pmu_elpg_statistics)(struct gk20a *g, u32 pg_engine_id,
836 struct pmu_pg_stats_data *pg_stat_data);
837 int (*pmu_pg_init_param)(struct gk20a *g, u32 pg_engine_id);
838 int (*pmu_pg_set_sub_feature_mask)(struct gk20a *g,
839 u32 pg_engine_id);
840 u32 (*pmu_pg_supported_engines_list)(struct gk20a *g);
841 u32 (*pmu_pg_engines_feature_list)(struct gk20a *g,
842 u32 pg_engine_id);
843 bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g,
844 u32 feature_id);
845 int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
846 int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock);
847 u32 (*pmu_pg_param_post_init)(struct gk20a *g);
848 void (*dump_secure_fuses)(struct gk20a *g);
849 int (*reset_engine)(struct gk20a *g, bool do_reset);
850 bool (*is_engine_in_reset)(struct gk20a *g);
851 int (*falcon_wait_for_halt)(struct gk20a *g,
852 unsigned int timeout);
853 int (*falcon_clear_halt_interrupt_status)(struct gk20a *g,
854 unsigned int timeout);
855 int (*init_falcon_setup_hw)(struct gk20a *g,
856 void *desc, u32 bl_sz);
857 bool (*is_lazy_bootstrap)(u32 falcon_id);
858 bool (*is_priv_load)(u32 falcon_id);
859 void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf);
860 int (*alloc_blob_space)(struct gk20a *g,
861 size_t size, struct nvgpu_mem *mem);
862 int (*pmu_populate_loader_cfg)(struct gk20a *g,
863 void *lsfm, u32 *p_bl_gen_desc_size);
864 int (*flcn_populate_bl_dmem_desc)(struct gk20a *g,
865 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
866 void (*handle_ext_irq)(struct gk20a *g, u32 intr);
867 void (*set_irqmask)(struct gk20a *g);
868 } pmu;
869 struct {
870 int (*init_debugfs)(struct gk20a *g);
871 void (*disable_slowboot)(struct gk20a *g);
872 int (*init_clk_support)(struct gk20a *g);
873 int (*suspend_clk_support)(struct gk20a *g);
874 u32 (*get_crystal_clk_hz)(struct gk20a *g);
875 unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain);
876 unsigned long (*get_rate)(struct gk20a *g, u32 api_domain);
877 int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate);
878 unsigned long (*get_fmax_at_vmin_safe)(struct clk_gk20a *clk);
879 u32 (*get_ref_clock_rate)(struct gk20a *g);
880 int (*predict_mv_at_hz_cur_tfloor)(struct clk_gk20a *clk,
881 unsigned long rate);
882 unsigned long (*get_maxrate)(struct gk20a *g, u32 api_domain);
883 int (*prepare_enable)(struct clk_gk20a *clk);
884 void (*disable_unprepare)(struct clk_gk20a *clk);
885 int (*get_voltage)(struct clk_gk20a *clk, u64 *val);
886 int (*get_gpcclk_clock_counter)(struct clk_gk20a *clk, u64 *val);
887 int (*pll_reg_write)(struct gk20a *g, u32 reg, u32 val);
888 int (*get_pll_debug_data)(struct gk20a *g,
889 struct nvgpu_clk_pll_debug_data *d);
890 int (*mclk_init)(struct gk20a *g);
891 void (*mclk_deinit)(struct gk20a *g);
892 int (*mclk_change)(struct gk20a *g, u16 val);
893 } clk;
894 struct {
895 u32 (*get_arbiter_clk_domains)(struct gk20a *g);
896 int (*get_arbiter_clk_range)(struct gk20a *g, u32 api_domain,
897 u16 *min_mhz, u16 *max_mhz);
898 int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain,
899 u16 *default_mhz);
900 /* This function is inherently unsafe to call while
901 * arbiter is running arbiter must be blocked
902 * before calling this function */
903 int (*get_current_pstate)(struct gk20a *g);
904 } clk_arb;
905 struct {
906 int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg);
907 } perf;
908 struct {
909 const struct regop_offset_range* (
910 *get_global_whitelist_ranges)(void);
911 int (*get_global_whitelist_ranges_count)(void);
912 const struct regop_offset_range* (
913 *get_context_whitelist_ranges)(void);
914 int (*get_context_whitelist_ranges_count)(void);
915 const u32* (*get_runcontrol_whitelist)(void);
916 int (*get_runcontrol_whitelist_count)(void);
917 const struct regop_offset_range* (
918 *get_runcontrol_whitelist_ranges)(void);
919 int (*get_runcontrol_whitelist_ranges_count)(void);
920 const u32* (*get_qctl_whitelist)(void);
921 int (*get_qctl_whitelist_count)(void);
922 const struct regop_offset_range* (
923 *get_qctl_whitelist_ranges)(void);
924 int (*get_qctl_whitelist_ranges_count)(void);
925 int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
926 } regops;
927 struct {
928 void (*intr_enable)(struct gk20a *g);
929 void (*intr_unit_config)(struct gk20a *g,
930 bool enable, bool is_stalling, u32 unit);
931 void (*isr_stall)(struct gk20a *g);
932 bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
933 u32 (*intr_stall)(struct gk20a *g);
934 void (*intr_stall_pause)(struct gk20a *g);
935 void (*intr_stall_resume)(struct gk20a *g);
936 u32 (*intr_nonstall)(struct gk20a *g);
937 void (*intr_nonstall_pause)(struct gk20a *g);
938 void (*intr_nonstall_resume)(struct gk20a *g);
939 void (*enable)(struct gk20a *g, u32 units);
940 void (*disable)(struct gk20a *g, u32 units);
941 void (*reset)(struct gk20a *g, u32 units);
942 u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
943 bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
944 } mc;
945 struct {
946 void (*show_dump)(struct gk20a *g,
947 struct gk20a_debug_output *o);
948 } debug;
949 struct {
950 int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s,
951 struct nvgpu_dbg_gpu_reg_op *ops,
952 u64 num_ops);
953 int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s,
954 bool disable_powergate);
955 bool (*check_and_set_global_reservation)(
956 struct dbg_session_gk20a *dbg_s,
957 struct dbg_profiler_object_data *prof_obj);
958 bool (*check_and_set_context_reservation)(
959 struct dbg_session_gk20a *dbg_s,
960 struct dbg_profiler_object_data *prof_obj);
961 void (*release_profiler_reservation)(
962 struct dbg_session_gk20a *dbg_s,
963 struct dbg_profiler_object_data *prof_obj);
964 int (*perfbuffer_enable)(struct gk20a *g, u64 offset, u32 size);
965 int (*perfbuffer_disable)(struct gk20a *g);
966 } dbg_session_ops;
967
968 int (*get_litter_value)(struct gk20a *g, int value);
969 int (*chip_init_gpu_characteristics)(struct gk20a *g);
970
971 struct {
972 void (*init_hw)(struct gk20a *g);
973 void (*isr)(struct gk20a *g);
974 int (*read_ptimer)(struct gk20a *g, u64 *value);
975 int (*get_timestamps_zipper)(struct gk20a *g,
976 u32 source_id, u32 count,
977 struct nvgpu_cpu_time_correlation_sample *);
978 int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
979 } bus;
980
981 struct {
982 int (*init)(struct gk20a *g);
983 int (*preos_wait_for_halt)(struct gk20a *g);
984 void (*preos_reload_check)(struct gk20a *g);
985 } bios;
986
987#if defined(CONFIG_GK20A_CYCLE_STATS)
988 struct {
989 int (*enable_snapshot)(struct channel_gk20a *ch,
990 struct gk20a_cs_snapshot_client *client);
991 void (*disable_snapshot)(struct gr_gk20a *gr);
992 int (*check_data_available)(struct channel_gk20a *ch,
993 u32 *pending,
994 bool *hw_overflow);
995 void (*set_handled_snapshots)(struct gk20a *g, u32 num);
996 u32 (*allocate_perfmon_ids)(struct gk20a_cs_snapshot *data,
997 u32 count);
998 u32 (*release_perfmon_ids)(struct gk20a_cs_snapshot *data,
999 u32 start,
1000 u32 count);
1001 int (*detach_snapshot)(struct channel_gk20a *ch,
1002 struct gk20a_cs_snapshot_client *client);
1003 } css;
1004#endif
1005 struct {
1006 int (*get_speed)(struct gk20a *g, u32 *xve_link_speed);
1007 int (*set_speed)(struct gk20a *g, u32 xve_link_speed);
1008 void (*available_speeds)(struct gk20a *g, u32 *speed_mask);
1009 u32 (*xve_readl)(struct gk20a *g, u32 reg);
1010 void (*xve_writel)(struct gk20a *g, u32 reg, u32 val);
1011 void (*disable_aspm)(struct gk20a *g);
1012 void (*reset_gpu)(struct gk20a *g);
1013#if defined(CONFIG_PCI_MSI)
1014 void (*rearm_msi)(struct gk20a *g);
1015#endif
1016 void (*enable_shadow_rom)(struct gk20a *g);
1017 void (*disable_shadow_rom)(struct gk20a *g);
1018 u32 (*get_link_control_status)(struct gk20a *g);
1019 } xve;
1020 struct {
1021 void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn);
1022 } falcon;
1023 struct {
1024 void (*isr)(struct gk20a *g);
1025 } priv_ring;
1026};
1027
1028struct nvgpu_bios_ucode {
1029 u8 *bootloader;
1030 u32 bootloader_phys_base;
1031 u32 bootloader_size;
1032 u8 *ucode;
1033 u32 phys_base;
1034 u32 size;
1035 u8 *dmem;
1036 u32 dmem_phys_base;
1037 u32 dmem_size;
1038 u32 code_entry_point;
1039};
1040
1041struct nvgpu_bios {
1042 u32 vbios_version;
1043 u8 vbios_oem_version;
1044
1045 u8 *data;
1046 size_t size;
1047
1048 struct nvgpu_bios_ucode devinit;
1049 struct nvgpu_bios_ucode preos;
1050
1051 u8 *devinit_tables;
1052 u32 devinit_tables_size;
1053 u8 *bootscripts;
1054 u32 bootscripts_size;
1055
1056 u8 mem_strap_data_count;
1057 u16 mem_strap_xlat_tbl_ptr;
1058
1059 u32 condition_table_ptr;
1060
1061 u32 devinit_tables_phys_base;
1062 u32 devinit_script_phys_base;
1063
1064 struct bit_token *perf_token;
1065 struct bit_token *clock_token;
1066 struct bit_token *virt_token;
1067 u32 expansion_rom_offset;
1068};
1069
1070struct nvgpu_gpu_params {
1071 /* GPU architecture ID */
1072 u32 gpu_arch;
1073 /* GPU implementation ID */
1074 u32 gpu_impl;
1075 /* GPU revision ID */
1076 u32 gpu_rev;
1077 /* sm version */
1078 u32 sm_arch_sm_version;
1079 /* sm instruction set */
1080 u32 sm_arch_spa_version;
1081 u32 sm_arch_warp_count;
1082};
1083
1084struct gk20a {
1085 void (*free)(struct gk20a *g);
1086 struct nvgpu_nvhost_dev *nvhost_dev;
1087
1088 /*
1089 * Used by <nvgpu/enabled.h>. Do not access directly!
1090 */
1091 unsigned long *enabled_flags;
1092
1093 nvgpu_atomic_t usage_count;
1094
1095 struct nvgpu_ref refcount;
1096
1097 const char *name;
1098
1099 bool gpu_reset_done;
1100 bool power_on;
1101 bool suspended;
1102
1103 u32 log_mask;
1104 u32 log_trace;
1105
1106 struct nvgpu_gpu_params params;
1107
1108 /*
1109 * Guards access to hardware when usual gk20a_{busy,idle} are skipped
1110 * for submits and held for channel lifetime but dropped for an ongoing
1111 * gk20a_do_idle().
1112 */
1113 struct nvgpu_rwsem deterministic_busy;
1114
1115 struct nvgpu_falcon pmu_flcn;
1116 struct nvgpu_falcon sec2_flcn;
1117 struct nvgpu_falcon fecs_flcn;
1118 struct nvgpu_falcon gpccs_flcn;
1119 struct nvgpu_falcon nvdec_flcn;
1120 struct clk_gk20a clk;
1121 struct fifo_gk20a fifo;
1122 struct gr_gk20a gr;
1123 struct sim_gk20a sim;
1124 struct mm_gk20a mm;
1125 struct nvgpu_pmu pmu;
1126 struct acr_desc acr;
1127 struct ecc_gk20a ecc;
1128#ifdef CONFIG_ARCH_TEGRA_18x_SOC
1129 struct clk_pmupstate clk_pmu;
1130 struct perf_pmupstate perf_pmu;
1131 struct pmgr_pmupstate pmgr_pmu;
1132 struct therm_pmupstate therm_pmu;
1133#endif
1134
1135#ifdef CONFIG_DEBUG_FS
1136 struct railgate_stats pstats;
1137#endif
1138 u32 gr_idle_timeout_default;
1139 bool timeouts_enabled;
1140 unsigned int ch_wdt_timeout_ms;
1141
1142 struct nvgpu_mutex poweron_lock;
1143 struct nvgpu_mutex poweroff_lock;
1144
1145 /* Channel priorities */
1146 u32 timeslice_low_priority_us;
1147 u32 timeslice_medium_priority_us;
1148 u32 timeslice_high_priority_us;
1149 u32 min_timeslice_us;
1150 u32 max_timeslice_us;
1151 bool runlist_interleave;
1152
1153 bool slcg_enabled;
1154 bool blcg_enabled;
1155 bool elcg_enabled;
1156 bool elpg_enabled;
1157 bool aelpg_enabled;
1158 bool can_elpg;
1159 bool mscg_enabled;
1160 bool forced_idle;
1161 bool forced_reset;
1162 bool allow_all;
1163
1164 u32 default_pri_timeout;
1165
1166 u32 ptimer_src_freq;
1167
1168 bool can_railgate;
1169 bool user_railgate_disabled;
1170 int railgate_delay;
1171
1172 unsigned int aggressive_sync_destroy_thresh;
1173 bool aggressive_sync_destroy;
1174
1175 bool has_syncpoints;
1176 /* Debugfs knob for forcing syncpt support off in runtime. */
1177 u32 disable_syncpoints;
1178
1179 bool support_pmu;
1180 u32 bootstrap_owner;
1181
1182 bool is_virtual;
1183
1184 u32 emc3d_ratio;
1185
1186 struct nvgpu_spinlock ltc_enabled_lock;
1187
1188 struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
1189
1190 /*
1191 * A group of semaphore pools. One for each channel.
1192 */
1193 struct nvgpu_semaphore_sea *sema_sea;
1194
1195 /* List of pending SW semaphore waits. */
1196 struct nvgpu_list_node pending_sema_waits;
1197 struct nvgpu_raw_spinlock pending_sema_waits_lock;
1198
1199 /* held while manipulating # of debug/profiler sessions present */
1200 /* also prevents debug sessions from attaching until released */
1201 struct nvgpu_mutex dbg_sessions_lock;
1202 int dbg_powergating_disabled_refcount; /*refcount for pg disable */
1203 int dbg_timeout_disabled_refcount; /*refcount for timeout disable */
1204
1205 /* must have dbg_sessions_lock before use */
1206 struct nvgpu_dbg_gpu_reg_op *dbg_regops_tmp_buf;
1207 u32 dbg_regops_tmp_buf_ops;
1208
1209 /* For perfbuf mapping */
1210 struct {
1211 struct dbg_session_gk20a *owner;
1212 u64 offset;
1213 } perfbuf;
1214
1215 /* For profiler reservations */
1216 struct nvgpu_list_node profiler_objects;
1217 bool global_profiler_reservation_held;
1218 int profiler_reservation_count;
1219
1220 void (*remove_support)(struct gk20a *);
1221
1222 u64 pg_ingating_time_us;
1223 u64 pg_ungating_time_us;
1224 u32 pg_gating_cnt;
1225
1226 struct nvgpu_spinlock mc_enable_lock;
1227
1228 struct gk20a_as as;
1229
1230 struct nvgpu_mutex client_lock;
1231 int client_refcount; /* open channels and ctrl nodes */
1232
1233 struct gpu_ops ops;
1234 u32 mc_intr_mask_restore[4];
1235 /*used for change of enum zbc update cmd id from ver 0 to ver1*/
1236 u32 pmu_ver_cmd_id_zbc_table_update;
1237 u32 pmu_lsf_pmu_wpr_init_done;
1238 u32 pmu_lsf_loaded_falcon_id;
1239
1240 int irqs_enabled;
1241 int irq_stall; /* can be same as irq_nonstall in case of PCI */
1242 int irq_nonstall;
1243 u32 max_ltc_count;
1244 u32 ltc_count;
1245
1246 struct gk20a_channel_worker {
1247 struct nvgpu_thread poll_task;
1248 nvgpu_atomic_t put;
1249 struct nvgpu_cond wq;
1250 struct nvgpu_list_node items;
1251 struct nvgpu_spinlock items_lock;
1252 struct nvgpu_mutex start_lock;
1253 } channel_worker;
1254
1255 struct gk20a_scale_profile *scale_profile;
1256 unsigned long last_freq;
1257
1258 struct gk20a_ctxsw_trace *ctxsw_trace;
1259 struct gk20a_fecs_trace *fecs_trace;
1260
1261 bool mmu_debug_ctrl;
1262
1263 u32 tpc_fs_mask_user;
1264
1265 struct nvgpu_bios bios;
1266 bool bios_is_init;
1267
1268 struct nvgpu_clk_arb *clk_arb;
1269
1270 struct gk20a_ce_app ce_app;
1271
1272 /* PCI device identifier */
1273 u16 pci_vendor_id, pci_device_id;
1274 u16 pci_subsystem_vendor_id, pci_subsystem_device_id;
1275 u16 pci_class;
1276 u8 pci_revision;
1277
1278 /* PCIe power states. */
1279 bool xve_l0s;
1280 bool xve_l1;
1281
1282 /* Current warning temp in sfxp24.8 */
1283 s32 curr_warn_temp;
1284
1285#if defined(CONFIG_PCI_MSI)
1286 /* Check if msi is enabled */
1287 bool msi_enabled;
1288#endif
1289#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE
1290 struct nvgpu_mem_alloc_tracker *vmallocs;
1291 struct nvgpu_mem_alloc_tracker *kmallocs;
1292#endif
1293
1294 /* The minimum VBIOS version supported */
1295 u32 vbios_min_version;
1296
1297 /* memory training sequence and mclk switch scripts */
1298 u32 mem_config_idx;
1299
1300 u64 dma_memory_used;
1301
1302#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
1303 u64 syncpt_unit_base;
1304 size_t syncpt_unit_size;
1305 u32 syncpt_size;
1306#endif
1307 struct nvgpu_mem syncpt_mem;
1308
1309 struct nvgpu_list_node boardobj_head;
1310 struct nvgpu_list_node boardobjgrp_head;
1311};
1312
1313static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
1314{
1315 return g->timeouts_enabled ?
1316 g->gr_idle_timeout_default : ULONG_MAX;
1317}
1318
1319#define MULTICHAR_TAG(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
1320enum BAR0_DEBUG_OPERATION {
1321 BARO_ZERO_NOP = 0,
1322 OP_END = MULTICHAR_TAG('D', 'O', 'N', 'E'),
1323 BAR0_READ32 = MULTICHAR_TAG('0', 'R', '3', '2'),
1324 BAR0_WRITE32 = MULTICHAR_TAG('0', 'W', '3', '2'),
1325};
1326
1327struct share_buffer_head {
1328 enum BAR0_DEBUG_OPERATION operation;
1329/* size of the operation item */
1330 u32 size;
1331 u32 completed;
1332 u32 failed;
1333 u64 context;
1334 u64 completion_callback;
1335};
1336
1337struct gk20a_cyclestate_buffer_elem {
1338 struct share_buffer_head head;
1339/* in */
1340 u64 p_data;
1341 u64 p_done;
1342 u32 offset_bar0;
1343 u16 first_bit;
1344 u16 last_bit;
1345/* out */
1346/* keep 64 bits to be consistent */
1347 u64 data;
1348};
1349
1350/* operations that will need to be executed on non stall workqueue */
1351enum gk20a_nonstall_ops {
1352 gk20a_nonstall_ops_wakeup_semaphore = BIT(0), /* wake up semaphore */
1353 gk20a_nonstall_ops_post_events = BIT(1),
1354};
1355
1356/* register accessors */
1357void __nvgpu_check_gpu_state(struct gk20a *g);
1358void __gk20a_warn_on_no_regs(void);
1359
1360/* convenience */
1361static inline struct gk20a *gk20a_from_as(struct gk20a_as *as)
1362{
1363 return container_of(as, struct gk20a, as);
1364}
1365static inline struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu)
1366{
1367 return container_of(pmu, struct gk20a, pmu);
1368}
1369
1370static inline u32 u64_hi32(u64 n)
1371{
1372 return (u32)((n >> 32) & ~(u32)0);
1373}
1374
1375static inline u32 u64_lo32(u64 n)
1376{
1377 return (u32)(n & ~(u32)0);
1378}
1379
1380static inline u64 hi32_lo32_to_u64(u32 hi, u32 lo)
1381{
1382 return (((u64)hi) << 32) | (u64)lo;
1383}
1384
1385static inline u32 set_field(u32 val, u32 mask, u32 field)
1386{
1387 return ((val & ~mask) | field);
1388}
1389
1390static inline u32 get_field(u32 reg, u32 mask)
1391{
1392 return (reg & mask);
1393}
1394
1395/* invalidate channel lookup tlb */
1396static inline void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr)
1397{
1398 nvgpu_spinlock_acquire(&gr->ch_tlb_lock);
1399 memset(gr->chid_tlb, 0,
1400 sizeof(struct gr_channel_map_tlb_entry) *
1401 GR_CHANNEL_MAP_TLB_SIZE);
1402 nvgpu_spinlock_release(&gr->ch_tlb_lock);
1403}
1404
1405/* classes that the device supports */
1406/* TBD: get these from an open-sourced SDK? */
1407enum {
1408 KEPLER_C = 0xA297,
1409 FERMI_TWOD_A = 0x902D,
1410 KEPLER_COMPUTE_A = 0xA0C0,
1411 KEPLER_INLINE_TO_MEMORY_A = 0xA040,
1412 KEPLER_DMA_COPY_A = 0xA0B5,
1413 KEPLER_CHANNEL_GPFIFO_C = 0xA26F,
1414};
1415
1416#define GK20A_BAR0_IORESOURCE_MEM 0
1417#define GK20A_BAR1_IORESOURCE_MEM 1
1418#define GK20A_SIM_IORESOURCE_MEM 2
1419
1420void gk20a_busy_noresume(struct gk20a *g);
1421void gk20a_idle_nosuspend(struct gk20a *g);
1422int __must_check gk20a_busy(struct gk20a *g);
1423void gk20a_idle(struct gk20a *g);
1424int __gk20a_do_idle(struct gk20a *g, bool force_reset);
1425int __gk20a_do_unidle(struct gk20a *g);
1426
1427int gk20a_can_busy(struct gk20a *g);
1428int gk20a_wait_for_idle(struct gk20a *g);
1429
1430#define NVGPU_GPU_ARCHITECTURE_SHIFT 4
1431
1432/* constructs unique and compact GPUID from nvgpu_gpu_characteristics
1433 * arch/impl fields */
1434#define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl)))
1435
1436#define GK20A_GPUID_GK20A 0x000000EA
1437#define GK20A_GPUID_GM20B 0x0000012B
1438#define GK20A_GPUID_GM20B_B 0x0000012E
1439#define NVGPU_GPUID_GP10B 0x0000013B
1440#define NVGPU_GPUID_GP104 0x00000134
1441#define NVGPU_GPUID_GP106 0x00000136
1442
1443int gk20a_init_gpu_characteristics(struct gk20a *g);
1444
1445static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq)
1446{
1447 return (u32)(((u64)(PTIMER_REF_FREQ_HZ * 10)) / ptimer_src_freq);
1448}
1449static inline u32 scale_ptimer(u32 timeout , u32 scale10x)
1450{
1451 if (((timeout*10) % scale10x) >= (scale10x/2))
1452 return ((timeout * 10) / scale10x) + 1;
1453 else
1454 return (timeout * 10) / scale10x;
1455}
1456
1457int gk20a_prepare_poweroff(struct gk20a *g);
1458int gk20a_finalize_poweron(struct gk20a *g);
1459
1460void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
1461
1462struct gk20a * __must_check gk20a_get(struct gk20a *g);
1463void gk20a_put(struct gk20a *g);
1464
1465static inline bool gk20a_platform_has_syncpoints(struct gk20a *g)
1466{
1467#ifdef CONFIG_TEGRA_GK20A_NVHOST
1468 return g->has_syncpoints && !g->disable_syncpoints;
1469#else
1470 return false;
1471#endif
1472}
1473
1474#endif /* GK20A_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 16:11:59 -0400