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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h10
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 47fd3aef..19ea76cb 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -656,9 +656,6 @@ struct gpu_ops {
656 u8 value); 656 u8 value);
657 void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg, 657 void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg,
658 u8 value); 658 u8 value);
659 /*used for change of enum zbc update cmd id from ver 0 to ver1*/
660 u32 cmd_id_zbc_table_update;
661 bool is_pmu_zbc_save_supported;
662 } pmu_ver; 659 } pmu_ver;
663 struct { 660 struct {
664 int (*get_netlist_name)(struct gk20a *g, int index, char *name); 661 int (*get_netlist_name)(struct gk20a *g, int index, char *name);
@@ -822,9 +819,6 @@ struct gpu_ops {
822 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); 819 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
823 void (*handle_ext_irq)(struct gk20a *g, u32 intr); 820 void (*handle_ext_irq)(struct gk20a *g, u32 intr);
824 void (*set_irqmask)(struct gk20a *g); 821 void (*set_irqmask)(struct gk20a *g);
825 u32 lspmuwprinitdone;
826 u32 lsfloadedfalconid;
827 bool fecsbootstrapdone;
828 } pmu; 822 } pmu;
829 struct { 823 struct {
830 int (*init_debugfs)(struct gk20a *g); 824 int (*init_debugfs)(struct gk20a *g);
@@ -1197,6 +1191,10 @@ struct gk20a {
1197 1191
1198 struct gpu_ops ops; 1192 struct gpu_ops ops;
1199 u32 mc_intr_mask_restore[4]; 1193 u32 mc_intr_mask_restore[4];
1194 /*used for change of enum zbc update cmd id from ver 0 to ver1*/
1195 u32 pmu_ver_cmd_id_zbc_table_update;
1196 u32 pmu_lsf_pmu_wpr_init_done;
1197 u32 pmu_lsf_loaded_falcon_id;
1200 1198
1201 int irqs_enabled; 1199 int irqs_enabled;
1202 int irq_stall; /* can be same as irq_nonstall in case of PCI */ 1200 int irq_stall; /* can be same as irq_nonstall in case of PCI */