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path: root/drivers/gpu/nvgpu/gk20a/gk20a.h
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h16
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 204fd371..5bb91f62 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -69,7 +69,6 @@ struct nvgpu_ctxsw_trace_filter;
69#include "fifo_gk20a.h" 69#include "fifo_gk20a.h"
70#include "tsg_gk20a.h" 70#include "tsg_gk20a.h"
71#include "pmu_gk20a.h" 71#include "pmu_gk20a.h"
72#include "therm_gk20a.h"
73#include "clk/clk.h" 72#include "clk/clk.h"
74#include "perf/perf.h" 73#include "perf/perf.h"
75#include "pmgr/pmgr.h" 74#include "pmgr/pmgr.h"
@@ -161,6 +160,18 @@ struct nvgpu_gpfifo_userdata {
161#define NVGPU_FB_MMU_FAULT_BUF_DISABLED 0U 160#define NVGPU_FB_MMU_FAULT_BUF_DISABLED 0U
162#define NVGPU_FB_MMU_FAULT_BUF_ENABLED 1U 161#define NVGPU_FB_MMU_FAULT_BUF_ENABLED 1U
163 162
163/* Parameters for init_elcg_mode/init_blcg_mode */
164enum {
165 ELCG_RUN, /* clk always run, i.e. disable elcg */
166 ELCG_STOP, /* clk is stopped */
167 ELCG_AUTO /* clk will run when non-idle, standard elcg mode */
168};
169
170enum {
171 BLCG_RUN, /* clk always run, i.e. disable blcg */
172 BLCG_AUTO /* clk will run when non-idle, standard blcg mode */
173};
174
164struct gpu_ops { 175struct gpu_ops {
165 struct { 176 struct {
166 int (*determine_L2_size_bytes)(struct gk20a *gk20a); 177 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
@@ -425,7 +436,6 @@ struct gpu_ops {
425 struct nvgpu_mem *mem, u64 gpu_va); 436 struct nvgpu_mem *mem, u64 gpu_va);
426 void (*set_preemption_buffer_va)(struct gk20a *g, 437 void (*set_preemption_buffer_va)(struct gk20a *g,
427 struct nvgpu_mem *mem, u64 gpu_va); 438 struct nvgpu_mem *mem, u64 gpu_va);
428 void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
429 void (*load_tpc_mask)(struct gk20a *g); 439 void (*load_tpc_mask)(struct gk20a *g);
430 int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); 440 int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch);
431 int (*trigger_suspend)(struct gk20a *g); 441 int (*trigger_suspend)(struct gk20a *g);
@@ -979,6 +989,8 @@ struct gpu_ops {
979 } pramin; 989 } pramin;
980 struct { 990 struct {
981 int (*init_therm_setup_hw)(struct gk20a *g); 991 int (*init_therm_setup_hw)(struct gk20a *g);
992 void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
993 void (*init_blcg_mode)(struct gk20a *g, u32 mode, u32 engine);
982 int (*elcg_init_idle_filters)(struct gk20a *g); 994 int (*elcg_init_idle_filters)(struct gk20a *g);
983#ifdef CONFIG_DEBUG_FS 995#ifdef CONFIG_DEBUG_FS
984 void (*therm_debugfs_init)(struct gk20a *g); 996 void (*therm_debugfs_init)(struct gk20a *g);