diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 31 |
1 files changed, 14 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ae640277..5429a570 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1,6 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * drivers/video/tegra/host/gk20a/gk20a.h | ||
3 | * | ||
4 | * GK20A Graphics | 2 | * GK20A Graphics |
5 | * | 3 | * |
6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. |
@@ -14,12 +12,11 @@ | |||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
15 | * more details. | 13 | * more details. |
16 | * | 14 | * |
17 | * You should have received a copy of the GNU General Public License along with | 15 | * You should have received a copy of the GNU General Public License |
18 | * this program; if not, write to the Free Software Foundation, Inc., | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
20 | */ | 17 | */ |
21 | #ifndef _NVHOST_GK20A_H_ | 18 | #ifndef GK20A_H |
22 | #define _NVHOST_GK20A_H_ | 19 | #define GK20A_H |
23 | 20 | ||
24 | 21 | ||
25 | struct gk20a; | 22 | struct gk20a; |
@@ -133,9 +130,9 @@ struct gpu_ops { | |||
133 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 130 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
134 | void (*free_channel_ctx)(struct channel_gk20a *c); | 131 | void (*free_channel_ctx)(struct channel_gk20a *c); |
135 | int (*alloc_obj_ctx)(struct channel_gk20a *c, | 132 | int (*alloc_obj_ctx)(struct channel_gk20a *c, |
136 | struct nvhost_alloc_obj_ctx_args *args); | 133 | struct nvgpu_alloc_obj_ctx_args *args); |
137 | int (*free_obj_ctx)(struct channel_gk20a *c, | 134 | int (*free_obj_ctx)(struct channel_gk20a *c, |
138 | struct nvhost_free_obj_ctx_args *args); | 135 | struct nvgpu_free_obj_ctx_args *args); |
139 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, | 136 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, |
140 | struct channel_gk20a *c, u64 zcull_va, | 137 | struct channel_gk20a *c, u64 zcull_va, |
141 | u32 mode); | 138 | u32 mode); |
@@ -405,7 +402,7 @@ struct gk20a { | |||
405 | 402 | ||
406 | spinlock_t mc_enable_lock; | 403 | spinlock_t mc_enable_lock; |
407 | 404 | ||
408 | struct nvhost_gpu_characteristics gpu_characteristics; | 405 | struct nvgpu_gpu_characteristics gpu_characteristics; |
409 | 406 | ||
410 | struct { | 407 | struct { |
411 | struct cdev cdev; | 408 | struct cdev cdev; |
@@ -504,11 +501,11 @@ struct gk20a_cyclestate_buffer_elem { | |||
504 | #ifdef CONFIG_DEBUG_FS | 501 | #ifdef CONFIG_DEBUG_FS |
505 | /* debug info, default is compiled-in but effectively disabled (0 mask) */ | 502 | /* debug info, default is compiled-in but effectively disabled (0 mask) */ |
506 | #define GK20A_DEBUG | 503 | #define GK20A_DEBUG |
507 | /*e.g: echo 1 > /d/tegra_host/dbg_mask */ | 504 | /*e.g: echo 1 > /d/gk20a.0/dbg_mask */ |
508 | #define GK20A_DEFAULT_DBG_MASK 0 | 505 | #define GK20A_DEFAULT_DBG_MASK 0 |
509 | #else | 506 | #else |
510 | /* manually enable and turn it on the mask */ | 507 | /* manually enable and turn it on the mask */ |
511 | /*#define NVHOST_DEBUG*/ | 508 | /*#define NVGPU_DEBUG*/ |
512 | #define GK20A_DEFAULT_DBG_MASK (dbg_info) | 509 | #define GK20A_DEFAULT_DBG_MASK (dbg_info) |
513 | #endif | 510 | #endif |
514 | 511 | ||
@@ -719,21 +716,21 @@ int __gk20a_do_unidle(struct platform_device *pdev); | |||
719 | const struct firmware * | 716 | const struct firmware * |
720 | gk20a_request_firmware(struct gk20a *g, const char *fw_name); | 717 | gk20a_request_firmware(struct gk20a *g, const char *fw_name); |
721 | 718 | ||
722 | #define NVHOST_GPU_ARCHITECTURE_SHIFT 4 | 719 | #define NVGPU_GPU_ARCHITECTURE_SHIFT 4 |
723 | 720 | ||
724 | /* constructs unique and compact GPUID from nvhost_gpu_characteristics | 721 | /* constructs unique and compact GPUID from nvgpu_gpu_characteristics |
725 | * arch/impl fields */ | 722 | * arch/impl fields */ |
726 | #define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl))) | 723 | #define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl))) |
727 | 724 | ||
728 | #define GK20A_GPUID_GK20A \ | 725 | #define GK20A_GPUID_GK20A \ |
729 | GK20A_GPUID(NVHOST_GPU_ARCH_GK100, NVHOST_GPU_IMPL_GK20A) | 726 | GK20A_GPUID(NVGPU_GPU_ARCH_GK100, NVGPU_GPU_IMPL_GK20A) |
730 | 727 | ||
731 | #define GK20A_GPUID_GM20B \ | 728 | #define GK20A_GPUID_GM20B \ |
732 | GK20A_GPUID(NVHOST_GPU_ARCH_GM200, NVHOST_GPU_IMPL_GM20B) | 729 | GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B) |
733 | 730 | ||
734 | int gk20a_init_gpu_characteristics(struct gk20a *g); | 731 | int gk20a_init_gpu_characteristics(struct gk20a *g); |
735 | 732 | ||
736 | int gk20a_user_init(struct platform_device *dev); | 733 | int gk20a_user_init(struct platform_device *dev); |
737 | void gk20a_user_deinit(struct platform_device *dev); | 734 | void gk20a_user_deinit(struct platform_device *dev); |
738 | 735 | ||
739 | #endif /* _NVHOST_GK20A_H_ */ | 736 | #endif /* GK20A_H */ |