diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 57 |
1 files changed, 6 insertions, 51 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f228cce4..2f85bf96 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -201,7 +201,7 @@ struct gpu_ops { | |||
201 | struct gr_ctx_desc *gr_ctx); | 201 | struct gr_ctx_desc *gr_ctx); |
202 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, | 202 | void (*update_ctxsw_preemption_mode)(struct gk20a *g, |
203 | struct channel_ctx_gk20a *ch_ctx, | 203 | struct channel_ctx_gk20a *ch_ctx, |
204 | void *ctx_ptr); | 204 | struct mem_desc *mem); |
205 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, | 205 | int (*update_smpc_ctxsw_mode)(struct gk20a *g, |
206 | struct channel_gk20a *c, | 206 | struct channel_gk20a *c, |
207 | bool enable); | 207 | bool enable); |
@@ -221,7 +221,8 @@ struct gpu_ops { | |||
221 | int (*wait_empty)(struct gk20a *g, unsigned long end_jiffies, | 221 | int (*wait_empty)(struct gk20a *g, unsigned long end_jiffies, |
222 | u32 expect_delay); | 222 | u32 expect_delay); |
223 | void (*init_cyclestats)(struct gk20a *g); | 223 | void (*init_cyclestats)(struct gk20a *g); |
224 | void (*enable_cde_in_fecs)(void *ctx_ptr); | 224 | void (*enable_cde_in_fecs)(struct gk20a *g, |
225 | struct mem_desc *mem); | ||
225 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, | 226 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, |
226 | u64 sms, bool enable); | 227 | u64 sms, bool enable); |
227 | void (*bpt_reg_info)(struct gk20a *g, | 228 | void (*bpt_reg_info)(struct gk20a *g, |
@@ -484,7 +485,7 @@ struct gpu_ops { | |||
484 | void (*cbc_clean)(struct gk20a *g); | 485 | void (*cbc_clean)(struct gk20a *g); |
485 | void (*tlb_invalidate)(struct vm_gk20a *vm); | 486 | void (*tlb_invalidate)(struct vm_gk20a *vm); |
486 | void (*set_big_page_size)(struct gk20a *g, | 487 | void (*set_big_page_size)(struct gk20a *g, |
487 | void *inst_ptr, int size); | 488 | struct mem_desc *mem, int size); |
488 | u32 (*get_big_page_sizes)(void); | 489 | u32 (*get_big_page_sizes)(void); |
489 | u32 (*get_physical_addr_bits)(struct gk20a *g); | 490 | u32 (*get_physical_addr_bits)(struct gk20a *g); |
490 | int (*init_mm_setup_hw)(struct gk20a *g); | 491 | int (*init_mm_setup_hw)(struct gk20a *g); |
@@ -493,7 +494,8 @@ struct gpu_ops { | |||
493 | void (*remove_bar2_vm)(struct gk20a *g); | 494 | void (*remove_bar2_vm)(struct gk20a *g); |
494 | const struct gk20a_mmu_level * | 495 | const struct gk20a_mmu_level * |
495 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); | 496 | (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); |
496 | void (*init_pdb)(struct gk20a *g, void *inst_ptr, u64 pdb_addr); | 497 | void (*init_pdb)(struct gk20a *g, struct mem_desc *mem, |
498 | u64 pdb_addr); | ||
497 | u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, | 499 | u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, |
498 | u32 flags); | 500 | u32 flags); |
499 | int (*bar1_bind)(struct gk20a *g, u64 bar1_iova); | 501 | int (*bar1_bind)(struct gk20a *g, u64 bar1_iova); |
@@ -859,53 +861,6 @@ do { \ | |||
859 | #define gk20a_dbg_info(fmt, arg...) \ | 861 | #define gk20a_dbg_info(fmt, arg...) \ |
860 | gk20a_dbg(gpu_dbg_info, fmt, ##arg) | 862 | gk20a_dbg(gpu_dbg_info, fmt, ##arg) |
861 | 863 | ||
862 | /* mem access with dbg_mem logging */ | ||
863 | static inline u8 gk20a_mem_rd08(void *ptr, int b) | ||
864 | { | ||
865 | u8 _b = ((const u8 *)ptr)[b]; | ||
866 | #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM | ||
867 | gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u8)*b, _b); | ||
868 | #endif | ||
869 | return _b; | ||
870 | } | ||
871 | static inline u16 gk20a_mem_rd16(void *ptr, int s) | ||
872 | { | ||
873 | u16 _s = ((const u16 *)ptr)[s]; | ||
874 | #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM | ||
875 | gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u16)*s, _s); | ||
876 | #endif | ||
877 | return _s; | ||
878 | } | ||
879 | static inline u32 gk20a_mem_rd32(void *ptr, int w) | ||
880 | { | ||
881 | u32 _w = ((const u32 *)ptr)[w]; | ||
882 | #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM | ||
883 | gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr + sizeof(u32)*w, _w); | ||
884 | #endif | ||
885 | return _w; | ||
886 | } | ||
887 | static inline void gk20a_mem_wr08(void *ptr, int b, u8 data) | ||
888 | { | ||
889 | #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM | ||
890 | gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u8)*b, data); | ||
891 | #endif | ||
892 | ((u8 *)ptr)[b] = data; | ||
893 | } | ||
894 | static inline void gk20a_mem_wr16(void *ptr, int s, u16 data) | ||
895 | { | ||
896 | #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM | ||
897 | gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u16)*s, data); | ||
898 | #endif | ||
899 | ((u16 *)ptr)[s] = data; | ||
900 | } | ||
901 | static inline void gk20a_mem_wr32(void *ptr, int w, u32 data) | ||
902 | { | ||
903 | #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM | ||
904 | gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u32)*w, data); | ||
905 | #endif | ||
906 | ((u32 *)ptr)[w] = data; | ||
907 | } | ||
908 | |||
909 | void gk20a_init_clk_ops(struct gpu_ops *gops); | 864 | void gk20a_init_clk_ops(struct gpu_ops *gops); |
910 | 865 | ||
911 | /* register accessors */ | 866 | /* register accessors */ |