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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index ac1226fc..bdf3a168 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -41,6 +41,7 @@ struct nvgpu_nvhost_dev;
41struct nvgpu_cpu_time_correlation_sample; 41struct nvgpu_cpu_time_correlation_sample;
42struct nvgpu_mem_sgt; 42struct nvgpu_mem_sgt;
43struct nvgpu_warpstate; 43struct nvgpu_warpstate;
44struct nvgpu_clk_session;
44struct nvgpu_clk_arb; 45struct nvgpu_clk_arb;
45#ifdef CONFIG_GK20A_CTXSW_TRACE 46#ifdef CONFIG_GK20A_CTXSW_TRACE
46struct nvgpu_gpu_ctxsw_trace_filter; 47struct nvgpu_gpu_ctxsw_trace_filter;
@@ -1083,6 +1084,9 @@ struct gpu_ops {
1083 int (*init_clk_support)(struct gk20a *g); 1084 int (*init_clk_support)(struct gk20a *g);
1084 int (*suspend_clk_support)(struct gk20a *g); 1085 int (*suspend_clk_support)(struct gk20a *g);
1085 u32 (*get_crystal_clk_hz)(struct gk20a *g); 1086 u32 (*get_crystal_clk_hz)(struct gk20a *g);
1087 int (*clk_domain_get_f_points)(struct gk20a *g,
1088 u32 clkapidomain, u32 *pfpointscount,
1089 u16 *pfreqpointsinmhz);
1086 unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain); 1090 unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain);
1087 unsigned long (*get_rate)(struct gk20a *g, u32 api_domain); 1091 unsigned long (*get_rate)(struct gk20a *g, u32 api_domain);
1088 int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate); 1092 int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate);
@@ -1107,15 +1111,18 @@ struct gpu_ops {
1107 bool support_lpwr_pg; 1111 bool support_lpwr_pg;
1108 } clk; 1112 } clk;
1109 struct { 1113 struct {
1114 int (*arbiter_clk_init)(struct gk20a *g);
1110 u32 (*get_arbiter_clk_domains)(struct gk20a *g); 1115 u32 (*get_arbiter_clk_domains)(struct gk20a *g);
1111 int (*get_arbiter_clk_range)(struct gk20a *g, u32 api_domain, 1116 int (*get_arbiter_clk_range)(struct gk20a *g, u32 api_domain,
1112 u16 *min_mhz, u16 *max_mhz); 1117 u16 *min_mhz, u16 *max_mhz);
1113 int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain, 1118 int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain,
1114 u16 *default_mhz); 1119 u16 *default_mhz);
1120 void (*clk_arb_run_arbiter_cb)(struct nvgpu_clk_arb *arb);
1115 /* This function is inherently unsafe to call while 1121 /* This function is inherently unsafe to call while
1116 * arbiter is running arbiter must be blocked 1122 * arbiter is running arbiter must be blocked
1117 * before calling this function */ 1123 * before calling this function */
1118 int (*get_current_pstate)(struct gk20a *g); 1124 int (*get_current_pstate)(struct gk20a *g);
1125 void (*clk_arb_cleanup)(struct nvgpu_clk_arb *arb);
1119 } clk_arb; 1126 } clk_arb;
1120 struct { 1127 struct {
1121 int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); 1128 int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg);