1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 20baf9de..1a248dba 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -41,7 +41,7 @@ struct fifo_runlist_info_gk20a {
        u32  total_entries;
        bool stopped;
        bool support_tsg;
-        struct mutex mutex; /* protect channel preempt and runlist upate */
+        struct nvgpu_mutex mutex; /* protect channel preempt and runlist update */
 };
 enum {
@@ -120,18 +120,18 @@ struct fifo_gk20a {
        struct channel_gk20a *channel;
        /* zero-kref'd channels here */
        struct list_head free_chs;
-        struct mutex free_chs_mutex;
+        struct nvgpu_mutex free_chs_mutex;
-        struct mutex gr_reset_mutex;
+        struct nvgpu_mutex gr_reset_mutex;
        struct tsg_gk20a *tsg;
-        struct mutex tsg_inuse_mutex;
+        struct nvgpu_mutex tsg_inuse_mutex;
        void (*remove_support)(struct fifo_gk20a *);
        bool sw_ready;
        struct {
                /* share info between isrs and non-isr code */
                struct {
-                        struct mutex mutex;
+                        struct nvgpu_mutex mutex;
                } isr;
                struct {
                        u32 device_fatal_0;
@@ -147,7 +147,7 @@ struct fifo_gk20a {
        unsigned long deferred_fault_engines;
        bool deferred_reset_pending;
-        struct mutex deferred_reset_mutex;
+        struct nvgpu_mutex deferred_reset_mutex;
 };
 static inline const char *gk20a_fifo_interleave_level_name(u32 interleave_level)

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 20baf9de..1a248dba 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -41,7 +41,7 @@ struct fifo_runlist_info_gk20a {
41	u32 total_entries;	41	u32 total_entries;
42	bool stopped;	42	bool stopped;
43	bool support_tsg;	43	bool support_tsg;
44	struct mutex mutex; /* protect channel preempt and runlist upate */	44	struct nvgpu_mutex mutex; /* protect channel preempt and runlist update */
45	};	45	};
46		46
47	enum {	47	enum {
@@ -120,18 +120,18 @@ struct fifo_gk20a {
120	struct channel_gk20a *channel;	120	struct channel_gk20a *channel;
121	/* zero-kref'd channels here */	121	/* zero-kref'd channels here */
122	struct list_head free_chs;	122	struct list_head free_chs;
123	struct mutex free_chs_mutex;	123	struct nvgpu_mutex free_chs_mutex;
124	struct mutex gr_reset_mutex;	124	struct nvgpu_mutex gr_reset_mutex;
125		125
126	struct tsg_gk20a *tsg;	126	struct tsg_gk20a *tsg;
127	struct mutex tsg_inuse_mutex;	127	struct nvgpu_mutex tsg_inuse_mutex;
128		128
129	void (remove_support)(struct fifo_gk20a );	129	void (remove_support)(struct fifo_gk20a );
130	bool sw_ready;	130	bool sw_ready;
131	struct {	131	struct {
132	/* share info between isrs and non-isr code */	132	/* share info between isrs and non-isr code */
133	struct {	133	struct {
134	struct mutex mutex;	134	struct nvgpu_mutex mutex;
135	} isr;	135	} isr;
136	struct {	136	struct {
137	u32 device_fatal_0;	137	u32 device_fatal_0;
@@ -147,7 +147,7 @@ struct fifo_gk20a {
147		147
148	unsigned long deferred_fault_engines;	148	unsigned long deferred_fault_engines;
149	bool deferred_reset_pending;	149	bool deferred_reset_pending;
150	struct mutex deferred_reset_mutex;	150	struct nvgpu_mutex deferred_reset_mutex;
151	};	151	};
152		152
153	static inline const char *gk20a_fifo_interleave_level_name(u32 interleave_level)	153	static inline const char *gk20a_fifo_interleave_level_name(u32 interleave_level)