diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 884e4a02..fea46a0e 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1215,9 +1215,7 @@ void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | |||
1215 | 1215 | ||
1216 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | 1216 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) |
1217 | { | 1217 | { |
1218 | struct fifo_gk20a *f = NULL; | ||
1219 | u32 engine_enum = ENGINE_INVAL_GK20A; | 1218 | u32 engine_enum = ENGINE_INVAL_GK20A; |
1220 | u32 inst_id = 0; | ||
1221 | struct fifo_engine_info_gk20a *engine_info; | 1219 | struct fifo_engine_info_gk20a *engine_info; |
1222 | 1220 | ||
1223 | gk20a_dbg_fn(""); | 1221 | gk20a_dbg_fn(""); |
@@ -1225,14 +1223,10 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) | |||
1225 | if (!g) | 1223 | if (!g) |
1226 | return; | 1224 | return; |
1227 | 1225 | ||
1228 | f = &g->fifo; | ||
1229 | |||
1230 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); | 1226 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); |
1231 | 1227 | ||
1232 | if (engine_info) { | 1228 | if (engine_info) |
1233 | engine_enum = engine_info->engine_enum; | 1229 | engine_enum = engine_info->engine_enum; |
1234 | inst_id = engine_info->inst_id; | ||
1235 | } | ||
1236 | 1230 | ||
1237 | if (engine_enum == ENGINE_INVAL_GK20A) | 1231 | if (engine_enum == ENGINE_INVAL_GK20A) |
1238 | nvgpu_err(g, "unsupported engine_id %d", engine_id); | 1232 | nvgpu_err(g, "unsupported engine_id %d", engine_id); |
@@ -1300,19 +1294,15 @@ bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, | |||
1300 | u32 engine_subid, bool fake_fault) | 1294 | u32 engine_subid, bool fake_fault) |
1301 | { | 1295 | { |
1302 | u32 engine_enum = ENGINE_INVAL_GK20A; | 1296 | u32 engine_enum = ENGINE_INVAL_GK20A; |
1303 | struct fifo_gk20a *fifo = NULL; | ||
1304 | struct fifo_engine_info_gk20a *engine_info; | 1297 | struct fifo_engine_info_gk20a *engine_info; |
1305 | 1298 | ||
1306 | if (!g) | 1299 | if (!g) |
1307 | return false; | 1300 | return false; |
1308 | 1301 | ||
1309 | fifo = &g->fifo; | ||
1310 | |||
1311 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); | 1302 | engine_info = gk20a_fifo_get_engine_info(g, engine_id); |
1312 | 1303 | ||
1313 | if (engine_info) { | 1304 | if (engine_info) |
1314 | engine_enum = engine_info->engine_enum; | 1305 | engine_enum = engine_info->engine_enum; |
1315 | } | ||
1316 | 1306 | ||
1317 | if (engine_enum == ENGINE_INVAL_GK20A) | 1307 | if (engine_enum == ENGINE_INVAL_GK20A) |
1318 | return false; | 1308 | return false; |
@@ -2974,7 +2964,6 @@ static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id) | |||
2974 | 2964 | ||
2975 | static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id) | 2965 | static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id) |
2976 | { | 2966 | { |
2977 | struct fifo_runlist_info_gk20a *runlist; | ||
2978 | struct nvgpu_timeout timeout; | 2967 | struct nvgpu_timeout timeout; |
2979 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; | 2968 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; |
2980 | int ret = -ETIMEDOUT; | 2969 | int ret = -ETIMEDOUT; |
@@ -2982,7 +2971,6 @@ static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id) | |||
2982 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), | 2971 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), |
2983 | NVGPU_TIMER_CPU_TIMER); | 2972 | NVGPU_TIMER_CPU_TIMER); |
2984 | 2973 | ||
2985 | runlist = &g->fifo.runlist_info[runlist_id]; | ||
2986 | do { | 2974 | do { |
2987 | if ((gk20a_readl(g, fifo_eng_runlist_r(runlist_id)) & | 2975 | if ((gk20a_readl(g, fifo_eng_runlist_r(runlist_id)) & |
2988 | fifo_eng_runlist_pending_true_f()) == 0) { | 2976 | fifo_eng_runlist_pending_true_f()) == 0) { |
@@ -3173,7 +3161,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3173 | struct fifo_runlist_info_gk20a *runlist = NULL; | 3161 | struct fifo_runlist_info_gk20a *runlist = NULL; |
3174 | u32 *runlist_entry_base = NULL; | 3162 | u32 *runlist_entry_base = NULL; |
3175 | u64 runlist_iova; | 3163 | u64 runlist_iova; |
3176 | u32 old_buf, new_buf; | 3164 | u32 new_buf; |
3177 | struct channel_gk20a *ch = NULL; | 3165 | struct channel_gk20a *ch = NULL; |
3178 | struct tsg_gk20a *tsg = NULL; | 3166 | struct tsg_gk20a *tsg = NULL; |
3179 | u32 count = 0; | 3167 | u32 count = 0; |
@@ -3205,7 +3193,6 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3205 | } | 3193 | } |
3206 | } | 3194 | } |
3207 | 3195 | ||
3208 | old_buf = runlist->cur_buffer; | ||
3209 | new_buf = !runlist->cur_buffer; | 3196 | new_buf = !runlist->cur_buffer; |
3210 | 3197 | ||
3211 | runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[new_buf]); | 3198 | runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[new_buf]); |