diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 44329a53..33ed9a04 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include "hw_pbdma_gk20a.h" | 31 | #include "hw_pbdma_gk20a.h" |
32 | #include "hw_ccsr_gk20a.h" | 32 | #include "hw_ccsr_gk20a.h" |
33 | #include "hw_ram_gk20a.h" | 33 | #include "hw_ram_gk20a.h" |
34 | #include "hw_proj_gk20a.h" | ||
35 | #include "hw_top_gk20a.h" | 34 | #include "hw_top_gk20a.h" |
36 | #include "hw_mc_gk20a.h" | 35 | #include "hw_mc_gk20a.h" |
37 | #include "hw_gr_gk20a.h" | 36 | #include "hw_gr_gk20a.h" |
@@ -349,6 +348,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
349 | u32 timeout; | 348 | u32 timeout; |
350 | int i; | 349 | int i; |
351 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 350 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
351 | u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); | ||
352 | 352 | ||
353 | gk20a_dbg_fn(""); | 353 | gk20a_dbg_fn(""); |
354 | /* enable pmc pfifo */ | 354 | /* enable pmc pfifo */ |
@@ -367,7 +367,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
367 | 367 | ||
368 | /* enable pbdma */ | 368 | /* enable pbdma */ |
369 | mask = 0; | 369 | mask = 0; |
370 | for (i = 0; i < proj_host_num_pbdma_v(); ++i) | 370 | for (i = 0; i < host_num_pbdma; ++i) |
371 | mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); | 371 | mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); |
372 | gk20a_writel(g, mc_enable_pb_r(), mask); | 372 | gk20a_writel(g, mc_enable_pb_r(), mask); |
373 | 373 | ||
@@ -378,7 +378,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
378 | 378 | ||
379 | /* enable pbdma interrupt */ | 379 | /* enable pbdma interrupt */ |
380 | mask = 0; | 380 | mask = 0; |
381 | for (i = 0; i < proj_host_num_pbdma_v(); i++) { | 381 | for (i = 0; i < host_num_pbdma; i++) { |
382 | intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); | 382 | intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); |
383 | intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f(); | 383 | intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f(); |
384 | gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); | 384 | gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); |
@@ -487,7 +487,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
487 | 487 | ||
488 | f->num_channels = g->ops.fifo.get_num_fifos(g); | 488 | f->num_channels = g->ops.fifo.get_num_fifos(g); |
489 | f->num_runlist_entries = fifo_eng_runlist_length_max_v(); | 489 | f->num_runlist_entries = fifo_eng_runlist_length_max_v(); |
490 | f->num_pbdma = proj_host_num_pbdma_v(); | 490 | f->num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); |
491 | f->max_engines = ENGINE_INVAL_GK20A; | 491 | f->max_engines = ENGINE_INVAL_GK20A; |
492 | 492 | ||
493 | f->userd_entry_size = 1 << ram_userd_base_shift_v(); | 493 | f->userd_entry_size = 1 << ram_userd_base_shift_v(); |