summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 1727cf1d..d8a73a75 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -780,6 +780,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
780 /* resetting engine using mc_enable_r() is not 780 /* resetting engine using mc_enable_r() is not
781 enough, we do full init sequence */ 781 enough, we do full init sequence */
782 gk20a_gr_reset(g); 782 gk20a_gr_reset(g);
783 gk20a_pmu_enable_elpg(g);
783 } 784 }
784 if (engine_id == top_device_info_type_enum_copy0_v()) 785 if (engine_id == top_device_info_type_enum_copy0_v())
785 gk20a_reset(g, mc_enable_ce2_m()); 786 gk20a_reset(g, mc_enable_ce2_m());
@@ -1086,7 +1087,7 @@ static bool gk20a_fifo_handle_mmu_fault(
1086 " deferring channel recovery to channel free"); 1087 " deferring channel recovery to channel free");
1087 /* clear interrupt */ 1088 /* clear interrupt */
1088 gk20a_writel(g, fifo_intr_mmu_fault_id_r(), fault_id); 1089 gk20a_writel(g, fifo_intr_mmu_fault_id_r(), fault_id);
1089 return verbose; 1090 goto exit_enable;
1090 } 1091 }
1091 1092
1092 /* clear interrupt */ 1093 /* clear interrupt */
@@ -1101,6 +1102,7 @@ static bool gk20a_fifo_handle_mmu_fault(
1101 gr_gpfifo_ctl_access_enabled_f() | 1102 gr_gpfifo_ctl_access_enabled_f() |
1102 gr_gpfifo_ctl_semaphore_access_enabled_f()); 1103 gr_gpfifo_ctl_semaphore_access_enabled_f());
1103 1104
1105exit_enable:
1104 /* It is safe to enable ELPG again. */ 1106 /* It is safe to enable ELPG again. */
1105 if (support_gk20a_pmu(g->dev) && g->elpg_enabled) 1107 if (support_gk20a_pmu(g->dev) && g->elpg_enabled)
1106 gk20a_pmu_enable_elpg(g); 1108 gk20a_pmu_enable_elpg(g);