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path: root/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c26
1 files changed, 0 insertions, 26 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 1ea7d6b3..648a8c86 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3962,32 +3962,6 @@ int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
3962 return channel_gk20a_set_schedule_params(ch); 3962 return channel_gk20a_set_schedule_params(ch);
3963} 3963}
3964 3964
3965int gk20a_fifo_set_priority(struct channel_gk20a *ch, u32 priority)
3966{
3967 if (gk20a_is_channel_marked_as_tsg(ch)) {
3968 nvgpu_err(ch->g, "invalid operation for TSG!");
3969 return -EINVAL;
3970 }
3971
3972 /* set priority of graphics channel */
3973 switch (priority) {
3974 case NVGPU_PRIORITY_LOW:
3975 ch->timeslice_us = ch->g->timeslice_low_priority_us;
3976 break;
3977 case NVGPU_PRIORITY_MEDIUM:
3978 ch->timeslice_us = ch->g->timeslice_medium_priority_us;
3979 break;
3980 case NVGPU_PRIORITY_HIGH:
3981 ch->timeslice_us = ch->g->timeslice_high_priority_us;
3982 break;
3983 default:
3984 pr_err("Unsupported priority");
3985 return -EINVAL;
3986 }
3987
3988 return channel_gk20a_set_schedule_params(ch);
3989}
3990
3991void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) 3965void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c)
3992{ 3966{
3993 struct gk20a *g = c->g; 3967 struct gk20a *g = c->g;