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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c54
1 files changed, 54 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 0c3e8039..aada3065 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -4077,6 +4077,60 @@ const char *gk20a_fifo_interleave_level_name(u32 interleave_level)
4077 } 4077 }
4078} 4078}
4079 4079
4080u32 gk20a_fifo_get_sema_wait_cmd_size(void)
4081{
4082 return 8;
4083}
4084
4085u32 gk20a_fifo_get_sema_incr_cmd_size(void)
4086{
4087 return 10;
4088}
4089
4090void gk20a_fifo_add_sema_cmd(struct gk20a *g,
4091 struct nvgpu_semaphore *s, u64 sema_va,
4092 struct priv_cmd_entry *cmd,
4093 u32 off, bool acquire, bool wfi)
4094{
4095 nvgpu_log_fn(g, " ");
4096
4097 /* semaphore_a */
4098 nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004);
4099 /* offset_upper */
4100 nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32) & 0xff);
4101 /* semaphore_b */
4102 nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005);
4103 /* offset */
4104 nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffff);
4105
4106 if (acquire) {
4107 /* semaphore_c */
4108 nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006);
4109 /* payload */
4110 nvgpu_mem_wr32(g, cmd->mem, off++,
4111 nvgpu_semaphore_get_value(s));
4112 /* semaphore_d */
4113 nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007);
4114 /* operation: acq_geq, switch_en */
4115 nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12));
4116 } else {
4117 /* semaphore_c */
4118 nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006);
4119 /* payload */
4120 nvgpu_mem_wr32(g, cmd->mem, off++,
4121 nvgpu_semaphore_get_value(s));
4122 /* semaphore_d */
4123 nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007);
4124 /* operation: release, wfi */
4125 nvgpu_mem_wr32(g, cmd->mem, off++,
4126 0x2 | ((wfi ? 0x0 : 0x1) << 20));
4127 /* non_stall_int */
4128 nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008);
4129 /* ignored */
4130 nvgpu_mem_wr32(g, cmd->mem, off++, 0);
4131 }
4132}
4133
4080#ifdef CONFIG_TEGRA_GK20A_NVHOST 4134#ifdef CONFIG_TEGRA_GK20A_NVHOST
4081void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g, 4135void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g,
4082 struct priv_cmd_entry *cmd, u32 off, 4136 struct priv_cmd_entry *cmd, u32 off,