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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ecc_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/ecc_gk20a.h46
1 files changed, 31 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
index 57eec1e0..fba8ba7d 100644
--- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A ECC 2 * GK20A ECC
3 * 3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -33,10 +33,6 @@ struct gk20a_ecc_stat {
33#endif 33#endif
34}; 34};
35 35
36#ifdef CONFIG_TEGRA_19x_GPU
37#include "ecc_t19x.h"
38#endif
39
40struct ecc_gk20a { 36struct ecc_gk20a {
41 /* Stats per engine */ 37 /* Stats per engine */
42 struct { 38 struct {
@@ -56,24 +52,44 @@ struct ecc_gk20a {
56 struct gk20a_ecc_stat tex_unique_sec_pipe1_count; 52 struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
57 struct gk20a_ecc_stat tex_unique_ded_pipe1_count; 53 struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
58 54
59#ifdef CONFIG_TEGRA_19x_GPU 55 struct gk20a_ecc_stat sm_l1_tag_corrected_err_count;
60 struct ecc_gr_t19x t19x; 56 struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count;
61#endif 57 struct gk20a_ecc_stat sm_cbu_corrected_err_count;
58 struct gk20a_ecc_stat sm_cbu_uncorrected_err_count;
59 struct gk20a_ecc_stat sm_l1_data_corrected_err_count;
60 struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count;
61 struct gk20a_ecc_stat sm_icache_corrected_err_count;
62 struct gk20a_ecc_stat sm_icache_uncorrected_err_count;
63 struct gk20a_ecc_stat gcc_l15_corrected_err_count;
64 struct gk20a_ecc_stat gcc_l15_uncorrected_err_count;
65 struct gk20a_ecc_stat fecs_corrected_err_count;
66 struct gk20a_ecc_stat fecs_uncorrected_err_count;
67 struct gk20a_ecc_stat gpccs_corrected_err_count;
68 struct gk20a_ecc_stat gpccs_uncorrected_err_count;
69 struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count;
70 struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count;
62 } gr; 71 } gr;
63 72
64 struct { 73 struct {
65 struct gk20a_ecc_stat l2_sec_count; 74 struct gk20a_ecc_stat l2_sec_count;
66 struct gk20a_ecc_stat l2_ded_count; 75 struct gk20a_ecc_stat l2_ded_count;
67#ifdef CONFIG_TEGRA_19x_GPU 76 struct gk20a_ecc_stat l2_cache_corrected_err_count;
68 struct ecc_ltc_t19x t19x; 77 struct gk20a_ecc_stat l2_cache_uncorrected_err_count;
69#endif
70 } ltc; 78 } ltc;
71 79
72 struct { 80 struct {
73#ifdef CONFIG_TEGRA_19x_GPU 81 struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count;
74 struct ecc_eng_t19x t19x; 82 struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count;
75#endif 83 struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count;
76 } eng; 84 struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count;
85 struct gk20a_ecc_stat mmu_fillunit_corrected_err_count;
86 struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count;
87 } fb;
88
89 struct {
90 struct gk20a_ecc_stat pmu_corrected_err_count;
91 struct gk20a_ecc_stat pmu_uncorrected_err_count;
92 } pmu;
77 93
78}; 94};
79 95