summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/debug_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/debug_gk20a.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
index f1e1f98a..a57a3c74 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
@@ -381,22 +381,22 @@ void gk20a_debug_init(struct device *dev)
381 if (platform->debugfs) { 381 if (platform->debugfs) {
382 platform->debugfs_alias = 382 platform->debugfs_alias =
383 debugfs_create_symlink("gpu.0", NULL, dev_name(dev)); 383 debugfs_create_symlink("gpu.0", NULL, dev_name(dev));
384 }
385 384
386 debugfs_create_file("status", S_IRUGO, platform->debugfs, 385 debugfs_create_file("status", S_IRUGO, platform->debugfs,
387 dev, &gk20a_debug_fops); 386 dev, &gk20a_debug_fops);
388 debugfs_create_file("gr_status", S_IRUGO, platform->debugfs, 387 debugfs_create_file("gr_status", S_IRUGO, platform->debugfs,
389 dev, &gk20a_gr_debug_fops); 388 dev, &gk20a_gr_debug_fops);
390 debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, platform->debugfs, 389 debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR,
391 &gk20a_debug_trace_cmdbuf); 390 platform->debugfs, &gk20a_debug_trace_cmdbuf);
392 391
393 debugfs_create_u32("ch_wdt_timeout_ms", S_IRUGO|S_IWUSR, 392 debugfs_create_u32("ch_wdt_timeout_ms", S_IRUGO|S_IWUSR,
394 platform->debugfs, &platform->ch_wdt_timeout_ms); 393 platform->debugfs, &platform->ch_wdt_timeout_ms);
395 394
396#if defined(GK20A_DEBUG) 395#if defined(GK20A_DEBUG)
397 debugfs_create_u32("dbg_mask", S_IRUGO|S_IWUSR, platform->debugfs, 396 debugfs_create_u32("dbg_mask", S_IRUGO|S_IWUSR,
398 &gk20a_dbg_mask); 397 platform->debugfs, &gk20a_dbg_mask);
399 debugfs_create_u32("dbg_ftrace", S_IRUGO|S_IWUSR, platform->debugfs, 398 debugfs_create_u32("dbg_ftrace", S_IRUGO|S_IWUSR,
400 &gk20a_dbg_ftrace); 399 platform->debugfs, &gk20a_dbg_ftrace);
401#endif 400#endif
401 }
402} 402}