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path: root/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c33
1 files changed, 1 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index 6af54e68..94486064 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -686,39 +686,8 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
686 "error (%d) during smpc ctxsw mode update\n", err); 686 "error (%d) during smpc ctxsw mode update\n", err);
687 goto clean_up; 687 goto clean_up;
688 } 688 }
689 /* The following regops are a hack/war to make up for the fact that we
690 * just scribbled into the ctxsw image w/o really knowing whether
691 * it was already swapped out in/out once or not, etc.
692 */
693 {
694 struct nvgpu_dbg_gpu_reg_op ops[4];
695 int i;
696 for (i = 0; i < ARRAY_SIZE(ops); i++) {
697 ops[i].op = NVGPU_DBG_GPU_REG_OP_WRITE_32;
698 ops[i].type = NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX;
699 ops[i].status = NVGPU_DBG_GPU_REG_OP_STATUS_SUCCESS;
700 ops[i].value_hi = 0;
701 ops[i].and_n_mask_lo = 0;
702 ops[i].and_n_mask_hi = 0;
703 }
704 /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/
705 ops[0].offset = 0x00419e08;
706 ops[0].value_lo = 0x1d;
707
708 /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */
709 ops[1].offset = 0x00419e58;
710 ops[1].value_lo = 0x1;
711 689
712 /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */ 690 err = g->ops.regops.apply_smpc_war(dbg_s);
713 ops[2].offset = 0x00419e68;
714 ops[2].value_lo = 0xaaaa;
715
716 /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */
717 ops[3].offset = 0x00419f40;
718 ops[3].value_lo = 0x18;
719
720 err = dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops));
721 }
722 691
723 clean_up: 692 clean_up:
724 mutex_unlock(&g->dbg_sessions_lock); 693 mutex_unlock(&g->dbg_sessions_lock);