diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 59 |
1 files changed, 9 insertions, 50 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 3c668013..536f00e0 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -329,62 +329,21 @@ static int nvgpu_gpu_ioctl_set_debug_mode( | |||
329 | struct gk20a *g, | 329 | struct gk20a *g, |
330 | struct nvgpu_gpu_sm_debug_mode_args *args) | 330 | struct nvgpu_gpu_sm_debug_mode_args *args) |
331 | { | 331 | { |
332 | int gpc, tpc, err = 0; | ||
333 | u32 sm_id, sm_dbgr_ctrl0; | ||
334 | struct channel_gk20a *ch; | 332 | struct channel_gk20a *ch; |
335 | struct nvgpu_dbg_gpu_reg_op ops; | 333 | int err; |
336 | u32 tpc_offset, gpc_offset, reg_offset; | ||
337 | 334 | ||
338 | ch = gk20a_get_channel_from_file(args->channel_fd); | 335 | ch = gk20a_get_channel_from_file(args->channel_fd); |
336 | if (!ch) | ||
337 | return -EINVAL; | ||
339 | 338 | ||
340 | mutex_lock(&g->dbg_sessions_lock); | 339 | mutex_lock(&g->dbg_sessions_lock); |
341 | 340 | if (g->ops.gr.set_sm_debug_mode) | |
342 | for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { | 341 | err = g->ops.gr.set_sm_debug_mode(g, ch, |
343 | if (args->sms & (1 << sm_id)) { | 342 | args->sms, !!args->enable); |
344 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | 343 | else |
345 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | 344 | err = -ENOSYS; |
346 | |||
347 | tpc_offset = proj_tpc_in_gpc_stride_v() * tpc; | ||
348 | gpc_offset = proj_gpc_stride_v() * gpc; | ||
349 | reg_offset = tpc_offset + gpc_offset; | ||
350 | |||
351 | ops.op = REGOP(READ_32); | ||
352 | ops.type = REGOP(TYPE_GR_CTX); | ||
353 | ops.status = REGOP(STATUS_SUCCESS); | ||
354 | ops.value_hi = 0; | ||
355 | ops.and_n_mask_lo = 0; | ||
356 | ops.and_n_mask_hi = 0; | ||
357 | ops.offset = gr_gpc0_tpc0_sm_dbgr_control0_r() + reg_offset; | ||
358 | |||
359 | err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 0, 1); | ||
360 | sm_dbgr_ctrl0 = ops.value_lo; | ||
361 | |||
362 | if (args->enable) { | ||
363 | sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, | ||
364 | gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(), | ||
365 | gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f()); | ||
366 | sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, | ||
367 | gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(), | ||
368 | gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f()); | ||
369 | sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, | ||
370 | gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(), | ||
371 | gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f()); | ||
372 | } else { | ||
373 | sm_dbgr_ctrl0 = set_field(sm_dbgr_ctrl0, | ||
374 | gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(), | ||
375 | gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f()); | ||
376 | } | ||
377 | |||
378 | if (!err) { | ||
379 | ops.op = REGOP(WRITE_32); | ||
380 | ops.value_lo = sm_dbgr_ctrl0; | ||
381 | err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0); | ||
382 | } else | ||
383 | gk20a_err(dev_from_gk20a(g), "Failed to access register\n"); | ||
384 | } | ||
385 | } | ||
386 | |||
387 | mutex_unlock(&g->dbg_sessions_lock); | 345 | mutex_unlock(&g->dbg_sessions_lock); |
346 | |||
388 | return err; | 347 | return err; |
389 | } | 348 | } |
390 | 349 | ||