diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 86 |
1 files changed, 51 insertions, 35 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 8e243eab..9082f861 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -76,7 +76,7 @@ int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp) | |||
76 | gk20a_dbg_fn(""); | 76 | gk20a_dbg_fn(""); |
77 | 77 | ||
78 | if (clk_session) | 78 | if (clk_session) |
79 | nvgpu_clk_arb_cleanup_session(g, clk_session); | 79 | nvgpu_clk_arb_release_session(g, clk_session); |
80 | kfree(priv); | 80 | kfree(priv); |
81 | 81 | ||
82 | return 0; | 82 | return 0; |
@@ -834,6 +834,8 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
834 | u32 i; | 834 | u32 i; |
835 | u32 max_points = 0; | 835 | u32 max_points = 0; |
836 | u32 num_points = 0; | 836 | u32 num_points = 0; |
837 | u64 min_hz; | ||
838 | u64 max_hz; | ||
837 | u16 min_mhz; | 839 | u16 min_mhz; |
838 | u16 max_mhz; | 840 | u16 max_mhz; |
839 | 841 | ||
@@ -862,7 +864,7 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
862 | return -EINVAL; | 864 | return -EINVAL; |
863 | 865 | ||
864 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, args->clk_domain, | 866 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, args->clk_domain, |
865 | &min_mhz, &max_mhz); | 867 | &min_hz, &max_hz); |
866 | if (err) | 868 | if (err) |
867 | return err; | 869 | return err; |
868 | 870 | ||
@@ -879,6 +881,8 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
879 | (uintptr_t)args->clk_vf_point_entries; | 881 | (uintptr_t)args->clk_vf_point_entries; |
880 | 882 | ||
881 | last_mhz = 0; | 883 | last_mhz = 0; |
884 | min_mhz = (u16)(min_hz / (u64)MHZ); | ||
885 | max_mhz = (u16)(max_hz / (u64)MHZ); | ||
882 | num_points = 0; | 886 | num_points = 0; |
883 | for (i = 0; (i < max_points) && !err; i++) { | 887 | for (i = 0; (i < max_points) && !err; i++) { |
884 | 888 | ||
@@ -891,7 +895,7 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
891 | continue; | 895 | continue; |
892 | 896 | ||
893 | last_mhz = fpoints[i]; | 897 | last_mhz = fpoints[i]; |
894 | clk_point.freq_mhz = fpoints[i]; | 898 | clk_point.freq_hz = (u64)fpoints[i] * (u64)MHZ; |
895 | 899 | ||
896 | err = copy_to_user((void __user *)entry, &clk_point, | 900 | err = copy_to_user((void __user *)entry, &clk_point, |
897 | sizeof(clk_point)); | 901 | sizeof(clk_point)); |
@@ -919,7 +923,6 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g, | |||
919 | u32 num_domains; | 923 | u32 num_domains; |
920 | u32 i; | 924 | u32 i; |
921 | int bit; | 925 | int bit; |
922 | u16 min_mhz, max_mhz; | ||
923 | int err; | 926 | int err; |
924 | 927 | ||
925 | gk20a_dbg_fn(""); | 928 | gk20a_dbg_fn(""); |
@@ -963,15 +966,13 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g, | |||
963 | clk_domains &= ~BIT(bit); | 966 | clk_domains &= ~BIT(bit); |
964 | } | 967 | } |
965 | 968 | ||
969 | clk_range.flags = 0; | ||
966 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, | 970 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, |
967 | clk_range.clk_domain, &min_mhz, &max_mhz); | 971 | clk_range.clk_domain, |
972 | &clk_range.min_hz, &clk_range.max_hz); | ||
968 | if (err) | 973 | if (err) |
969 | return err; | 974 | return err; |
970 | 975 | ||
971 | clk_range.min_mhz = min_mhz; | ||
972 | clk_range.max_mhz = max_mhz; | ||
973 | clk_range.flags = 0; | ||
974 | |||
975 | err = copy_to_user(entry, &clk_range, sizeof(clk_range)); | 976 | err = copy_to_user(entry, &clk_range, sizeof(clk_range)); |
976 | if (err) | 977 | if (err) |
977 | return -EFAULT; | 978 | return -EFAULT; |
@@ -992,7 +993,6 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
992 | struct nvgpu_clk_session *session = priv->clk_session; | 993 | struct nvgpu_clk_session *session = priv->clk_session; |
993 | u32 clk_domains = 0; | 994 | u32 clk_domains = 0; |
994 | u32 i; | 995 | u32 i; |
995 | int fd; | ||
996 | 996 | ||
997 | gk20a_dbg_fn(""); | 997 | gk20a_dbg_fn(""); |
998 | 998 | ||
@@ -1003,10 +1003,6 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1003 | if (!clk_domains) | 1003 | if (!clk_domains) |
1004 | return -EINVAL; | 1004 | return -EINVAL; |
1005 | 1005 | ||
1006 | fd = nvgpu_clk_arb_install_session_fd(g, session); | ||
1007 | if (fd < 0) | ||
1008 | return fd; | ||
1009 | |||
1010 | entry = (struct nvgpu_gpu_clk_info __user *) | 1006 | entry = (struct nvgpu_gpu_clk_info __user *) |
1011 | (uintptr_t)args->clk_info_entries; | 1007 | (uintptr_t)args->clk_info_entries; |
1012 | 1008 | ||
@@ -1031,16 +1027,12 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1031 | sizeof(clk_info))) | 1027 | sizeof(clk_info))) |
1032 | return -EFAULT; | 1028 | return -EFAULT; |
1033 | 1029 | ||
1034 | nvgpu_clk_arb_set_session_target_mhz(session, | 1030 | nvgpu_clk_arb_set_session_target_hz(session, |
1035 | clk_info.clk_domain, clk_info.target_mhz); | 1031 | clk_info.clk_domain, clk_info.freq_hz); |
1036 | } | 1032 | } |
1037 | 1033 | ||
1038 | nvgpu_clk_arb_apply_session_constraints(g, session); | 1034 | return nvgpu_clk_arb_apply_session_constraints(g, session, |
1039 | 1035 | &args->completion_fd); | |
1040 | args->req_nr = nvgpu_clk_arb_get_session_req_nr(g, session); | ||
1041 | args->fd = fd; | ||
1042 | |||
1043 | return 0; | ||
1044 | } | 1036 | } |
1045 | 1037 | ||
1046 | 1038 | ||
@@ -1053,8 +1045,6 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1053 | struct nvgpu_clk_session *session = priv->clk_session; | 1045 | struct nvgpu_clk_session *session = priv->clk_session; |
1054 | u32 clk_domains = 0; | 1046 | u32 clk_domains = 0; |
1055 | u32 num_domains; | 1047 | u32 num_domains; |
1056 | u16 actual_mhz; | ||
1057 | u16 target_mhz; | ||
1058 | u32 i; | 1048 | u32 i; |
1059 | int err; | 1049 | int err; |
1060 | int bit; | 1050 | int bit; |
@@ -1064,8 +1054,6 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1064 | if (!session) | 1054 | if (!session) |
1065 | return -EINVAL; | 1055 | return -EINVAL; |
1066 | 1056 | ||
1067 | args->last_req_nr = nvgpu_clk_arb_get_arbiter_req_nr(g); | ||
1068 | |||
1069 | if (!args->flags) { | 1057 | if (!args->flags) { |
1070 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); | 1058 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); |
1071 | num_domains = hweight_long(clk_domains); | 1059 | num_domains = hweight_long(clk_domains); |
@@ -1100,20 +1088,29 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1100 | bit = ffs(clk_domains) - 1; | 1088 | bit = ffs(clk_domains) - 1; |
1101 | clk_info.clk_domain = BIT(bit); | 1089 | clk_info.clk_domain = BIT(bit); |
1102 | clk_domains &= ~BIT(bit); | 1090 | clk_domains &= ~BIT(bit); |
1091 | clk_info.clk_type = args->clk_type; | ||
1103 | } | 1092 | } |
1104 | 1093 | ||
1105 | err = nvgpu_clk_arb_get_arbiter_actual_mhz(g, | 1094 | switch (clk_info.clk_type) { |
1106 | clk_info.clk_domain, &actual_mhz); | 1095 | case NVGPU_GPU_CLK_TYPE_TARGET: |
1107 | if (err) | 1096 | err = nvgpu_clk_arb_get_session_target_hz(session, |
1108 | return err; | 1097 | clk_info.clk_domain, &clk_info.freq_hz); |
1109 | 1098 | break; | |
1110 | err = nvgpu_clk_arb_get_session_target_mhz(session, | 1099 | case NVGPU_GPU_CLK_TYPE_ACTUAL: |
1111 | clk_info.clk_domain, &target_mhz); | 1100 | err = nvgpu_clk_arb_get_arbiter_actual_hz(g, |
1101 | clk_info.clk_domain, &clk_info.freq_hz); | ||
1102 | break; | ||
1103 | case NVGPU_GPU_CLK_TYPE_EFFECTIVE: | ||
1104 | err = nvgpu_clk_arb_get_arbiter_effective_hz(g, | ||
1105 | clk_info.clk_domain, &clk_info.freq_hz); | ||
1106 | break; | ||
1107 | default: | ||
1108 | err = -EINVAL; | ||
1109 | break; | ||
1110 | } | ||
1112 | if (err) | 1111 | if (err) |
1113 | return err; | 1112 | return err; |
1114 | 1113 | ||
1115 | clk_info.actual_mhz = actual_mhz; | ||
1116 | clk_info.target_mhz = target_mhz; | ||
1117 | clk_info.flags = 0; | 1114 | clk_info.flags = 0; |
1118 | 1115 | ||
1119 | err = copy_to_user((void __user *)entry, &clk_info, | 1116 | err = copy_to_user((void __user *)entry, &clk_info, |
@@ -1127,6 +1124,20 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1127 | return 0; | 1124 | return 0; |
1128 | } | 1125 | } |
1129 | 1126 | ||
1127 | static int nvgpu_gpu_clk_get_event_fd(struct gk20a *g, | ||
1128 | struct gk20a_ctrl_priv *priv, | ||
1129 | struct nvgpu_gpu_clk_get_event_fd_args *args) | ||
1130 | { | ||
1131 | struct nvgpu_clk_session *session = priv->clk_session; | ||
1132 | |||
1133 | gk20a_dbg_fn(""); | ||
1134 | |||
1135 | if (!session || args->flags) | ||
1136 | return -EINVAL; | ||
1137 | |||
1138 | return nvgpu_clk_arb_install_event_fd(g, session, &args->event_fd); | ||
1139 | } | ||
1140 | |||
1130 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | 1141 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) |
1131 | { | 1142 | { |
1132 | struct gk20a_ctrl_priv *priv = filp->private_data; | 1143 | struct gk20a_ctrl_priv *priv = filp->private_data; |
@@ -1409,6 +1420,11 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1409 | (struct nvgpu_gpu_clk_get_info_args *)buf); | 1420 | (struct nvgpu_gpu_clk_get_info_args *)buf); |
1410 | break; | 1421 | break; |
1411 | 1422 | ||
1423 | case NVGPU_GPU_IOCTL_CLK_GET_EVENT_FD: | ||
1424 | err = nvgpu_gpu_clk_get_event_fd(g, priv, | ||
1425 | (struct nvgpu_gpu_clk_get_event_fd_args *)buf); | ||
1426 | break; | ||
1427 | |||
1412 | default: | 1428 | default: |
1413 | dev_dbg(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd); | 1429 | dev_dbg(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd); |
1414 | err = -ENOTTY; | 1430 | err = -ENOTTY; |