1 files changed, 121 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h
new file mode 100644
index 00000000..2fd009df
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h
@@ -0,0 +1,121 @@
+/*
+ * drivers/video/tegra/host/gk20a/channel_sync_gk20a.h
+ *
+ * GK20A Channel Synchronization Abstraction
+ *
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _GK20A_CHANNEL_SYNC_H_
+#define _GK20A_CHANNEL_SYNC_H_
+struct gk20a_channel_sync;
+struct priv_cmd_entry;
+struct channel_gk20a;
+struct gk20a_fence;
+struct gk20a;
+struct gk20a_channel_sync {
+        nvgpu_atomic_t refcount;
+        /* Generate a gpu wait cmdbuf from syncpoint.
+         * Returns
+         *  - a gpu cmdbuf that performs the wait when executed,
+         *  - possibly a helper fence that the caller must hold until the
+         *    cmdbuf is executed.
+         */
+        int (*wait_syncpt)(struct gk20a_channel_sync *s, u32 id, u32 thresh,
+                           struct priv_cmd_entry *entry,
+                           struct gk20a_fence *fence);
+        /* Generate a gpu wait cmdbuf from sync fd.
+         * Returns
+         *  - a gpu cmdbuf that performs the wait when executed,
+         *  - possibly a helper fence that the caller must hold until the
+         *    cmdbuf is executed.
+         */
+        int (*wait_fd)(struct gk20a_channel_sync *s, int fd,
+                       struct priv_cmd_entry *entry,
+                       struct gk20a_fence *fence);
+        /* Increment syncpoint/semaphore.
+         * Returns
+         *  - a gpu cmdbuf that performs the increment when executed,
+         *  - a fence that can be passed to wait_cpu() and is_expired().
+         */
+        int (*incr)(struct gk20a_channel_sync *s,
+                    struct priv_cmd_entry *entry,
+                    struct gk20a_fence *fence,
+                    bool need_sync_fence,
+                    bool register_irq);
+        /* Increment syncpoint/semaphore, preceded by a wfi.
+         * Returns
+         *  - a gpu cmdbuf that performs the increment when executed,
+         *  - a fence that can be passed to wait_cpu() and is_expired().
+         */
+        int (*incr_wfi)(struct gk20a_channel_sync *s,
+                        struct priv_cmd_entry *entry,
+                        struct gk20a_fence *fence);
+        /* Increment syncpoint/semaphore, so that the returned fence represents
+         * work completion (may need wfi) and can be returned to user space.
+         * Returns
+         *  - a gpu cmdbuf that performs the increment when executed,
+         *  - a fence that can be passed to wait_cpu() and is_expired(),
+         *  - a gk20a_fence that signals when the incr has happened.
+         */
+        int (*incr_user)(struct gk20a_channel_sync *s,
+                         int wait_fence_fd,
+                         struct priv_cmd_entry *entry,
+                         struct gk20a_fence *fence,
+                         bool wfi,
+                         bool need_sync_fence,
+                         bool register_irq);
+        /* Reset the channel syncpoint/semaphore. */
+        void (*set_min_eq_max)(struct gk20a_channel_sync *s);
+        /* Signals the sync timeline (if owned by the gk20a_channel_sync layer).
+         * This should be called when we notice that a gk20a_fence is
+         * expired. */
+        void (*signal_timeline)(struct gk20a_channel_sync *s);
+        /* Returns the sync point id or negative number if no syncpt*/
+        int (*syncpt_id)(struct gk20a_channel_sync *s);
+        /* Free the resources allocated by gk20a_channel_sync_create. */
+        void (*destroy)(struct gk20a_channel_sync *s);
+};
+void gk20a_channel_sync_destroy(struct gk20a_channel_sync *sync);
+struct gk20a_channel_sync *gk20a_channel_sync_create(struct channel_gk20a *c);
+bool gk20a_channel_sync_needs_sync_framework(struct gk20a *g);
+#ifdef CONFIG_SYNC
+void gk20a_channel_cancel_pending_sema_waits(struct gk20a *g);
+#else
+static inline void gk20a_channel_cancel_pending_sema_waits(struct gk20a *g)
+{
+}
+#endif
+#endif

diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h new file mode 100644 index 00000000..2fd009df --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h
@@ -0,0 +1,121 @@
	1	/*
	2	* drivers/video/tegra/host/gk20a/channel_sync_gk20a.h
	3	*
	4	* GK20A Channel Synchronization Abstraction
	5	*
	6	* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	24	* DEALINGS IN THE SOFTWARE.
	25	*/
	26
	27	#ifndef _GK20A_CHANNEL_SYNC_H_
	28	#define _GK20A_CHANNEL_SYNC_H_
	29
	30	struct gk20a_channel_sync;
	31	struct priv_cmd_entry;
	32	struct channel_gk20a;
	33	struct gk20a_fence;
	34	struct gk20a;
	35
	36	struct gk20a_channel_sync {
	37	nvgpu_atomic_t refcount;
	38
	39	/* Generate a gpu wait cmdbuf from syncpoint.
	40	* Returns
	41	* - a gpu cmdbuf that performs the wait when executed,
	42	* - possibly a helper fence that the caller must hold until the
	43	* cmdbuf is executed.
	44	*/
	45	int (wait_syncpt)(struct gk20a_channel_sync s, u32 id, u32 thresh,
	46	struct priv_cmd_entry *entry,
	47	struct gk20a_fence *fence);
	48
	49	/* Generate a gpu wait cmdbuf from sync fd.
	50	* Returns
	51	* - a gpu cmdbuf that performs the wait when executed,
	52	* - possibly a helper fence that the caller must hold until the
	53	* cmdbuf is executed.
	54	*/
	55	int (wait_fd)(struct gk20a_channel_sync s, int fd,
	56	struct priv_cmd_entry *entry,
	57	struct gk20a_fence *fence);
	58
	59	/* Increment syncpoint/semaphore.
	60	* Returns
	61	* - a gpu cmdbuf that performs the increment when executed,
	62	* - a fence that can be passed to wait_cpu() and is_expired().
	63	*/
	64	int (incr)(struct gk20a_channel_sync s,
	65	struct priv_cmd_entry *entry,
	66	struct gk20a_fence *fence,
	67	bool need_sync_fence,
	68	bool register_irq);
	69
	70	/* Increment syncpoint/semaphore, preceded by a wfi.
	71	* Returns
	72	* - a gpu cmdbuf that performs the increment when executed,
	73	* - a fence that can be passed to wait_cpu() and is_expired().
	74	*/
	75	int (incr_wfi)(struct gk20a_channel_sync s,
	76	struct priv_cmd_entry *entry,
	77	struct gk20a_fence *fence);
	78
	79	/* Increment syncpoint/semaphore, so that the returned fence represents
	80	* work completion (may need wfi) and can be returned to user space.
	81	* Returns
	82	* - a gpu cmdbuf that performs the increment when executed,
	83	* - a fence that can be passed to wait_cpu() and is_expired(),
	84	* - a gk20a_fence that signals when the incr has happened.
	85	*/
	86	int (incr_user)(struct gk20a_channel_sync s,
	87	int wait_fence_fd,
	88	struct priv_cmd_entry *entry,
	89	struct gk20a_fence *fence,
	90	bool wfi,
	91	bool need_sync_fence,
	92	bool register_irq);
	93
	94	/* Reset the channel syncpoint/semaphore. */
	95	void (set_min_eq_max)(struct gk20a_channel_sync s);
	96
	97	/* Signals the sync timeline (if owned by the gk20a_channel_sync layer).
	98	* This should be called when we notice that a gk20a_fence is
	99	* expired. */
	100	void (signal_timeline)(struct gk20a_channel_sync s);
	101
	102	/* Returns the sync point id or negative number if no syncpt*/
	103	int (syncpt_id)(struct gk20a_channel_sync s);
	104
	105	/* Free the resources allocated by gk20a_channel_sync_create. */
	106	void (destroy)(struct gk20a_channel_sync s);
	107	};
	108
	109	void gk20a_channel_sync_destroy(struct gk20a_channel_sync *sync);
	110	struct gk20a_channel_sync gk20a_channel_sync_create(struct channel_gk20a c);
	111	bool gk20a_channel_sync_needs_sync_framework(struct gk20a *g);
	112
	113	#ifdef CONFIG_SYNC
	114	void gk20a_channel_cancel_pending_sema_waits(struct gk20a *g);
	115	#else
	116	static inline void gk20a_channel_cancel_pending_sema_waits(struct gk20a *g)
	117	{
	118	}
	119	#endif
	120
	121	#endif