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path: root/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 654388cb..9b1f2987 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -44,6 +44,9 @@
44 44
45#define NVGPU_BEGIN_AGGRESSIVE_SYNC_DESTROY_LIMIT 64 /* channels */ 45#define NVGPU_BEGIN_AGGRESSIVE_SYNC_DESTROY_LIMIT 64 /* channels */
46 46
47#define NVGPU_CHANNEL_MIN_TIMESLICE_US 1000
48#define NVGPU_CHANNEL_MAX_TIMESLICE_US 50000
49
47static struct channel_gk20a *allocate_channel(struct fifo_gk20a *f); 50static struct channel_gk20a *allocate_channel(struct fifo_gk20a *f);
48static void free_channel(struct fifo_gk20a *f, struct channel_gk20a *c); 51static void free_channel(struct fifo_gk20a *f, struct channel_gk20a *c);
49 52
@@ -2633,6 +2636,21 @@ int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority)
2633 timeslice_timeout); 2636 timeslice_timeout);
2634} 2637}
2635 2638
2639int gk20a_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
2640{
2641 if (gk20a_is_channel_marked_as_tsg(ch)) {
2642 gk20a_err(dev_from_gk20a(ch->g),
2643 "invalid operation for TSG!\n");
2644 return -EINVAL;
2645 }
2646
2647 if (timeslice < NVGPU_CHANNEL_MIN_TIMESLICE_US ||
2648 timeslice > NVGPU_CHANNEL_MAX_TIMESLICE_US)
2649 return -EINVAL;
2650
2651 return channel_gk20a_set_schedule_params(ch, timeslice);
2652}
2653
2636static int gk20a_channel_zcull_bind(struct channel_gk20a *ch, 2654static int gk20a_channel_zcull_bind(struct channel_gk20a *ch,
2637 struct nvgpu_zcull_bind_args *args) 2655 struct nvgpu_zcull_bind_args *args)
2638{ 2656{
@@ -2785,6 +2803,7 @@ void gk20a_init_channel(struct gpu_ops *gops)
2785 gops->fifo.free_inst = channel_gk20a_free_inst; 2803 gops->fifo.free_inst = channel_gk20a_free_inst;
2786 gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; 2804 gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc;
2787 gops->fifo.channel_set_priority = gk20a_channel_set_priority; 2805 gops->fifo.channel_set_priority = gk20a_channel_set_priority;
2806 gops->fifo.channel_set_timeslice = gk20a_channel_set_timeslice;
2788} 2807}
2789 2808
2790long gk20a_channel_ioctl(struct file *filp, 2809long gk20a_channel_ioctl(struct file *filp,
@@ -3047,6 +3066,18 @@ long gk20a_channel_ioctl(struct file *filp,
3047 ((struct nvgpu_runlist_interleave_args *)buf)->level); 3066 ((struct nvgpu_runlist_interleave_args *)buf)->level);
3048 gk20a_idle(dev); 3067 gk20a_idle(dev);
3049 break; 3068 break;
3069 case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE:
3070 err = gk20a_busy(dev);
3071 if (err) {
3072 dev_err(&dev->dev,
3073 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3074 __func__, cmd);
3075 break;
3076 }
3077 err = ch->g->ops.fifo.channel_set_timeslice(ch,
3078 ((struct nvgpu_timeslice_args *)buf)->timeslice_us);
3079 gk20a_idle(dev);
3080 break;
3050 default: 3081 default:
3051 dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd); 3082 dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd);
3052 err = -ENOTTY; 3083 err = -ENOTTY;